Implementing 128 Bit Persistent Addresses on 80x86 Processors
The Intel architecture for the 80x86 series machines lends itself well to the implementation of persistent object oriented languages. They are also by a wide margin the most commonly used CPUs in the world. Mass production has driven down the costs of machines using these processors and they thus make an appealing platform for experimentation.They have a model of store which corresponds well to the 7 layer model of persistent memory proposed by the authors: with physical, paged and segmented memory interfaces. One could map persistent objects directly onto Intel segments, but this would suffer from the small size of the segment identifier which only permits 16K of objects. For a distributed object oriented system one needs a much larger number of objects. The paper examines software and hardware techniques that can be used to map dynamically from network wide object identifiers to hardware supported segments. Four techniques are presented, two software and two hardware assisted techniques. The two software methods and one of the hardware methods have been implemented.
KeywordsAddress Space Virtual Memory Persistent Store Object Store Persistent Object
Unable to display preview. Download preview PDF.
- 1.Balch, P., Cockshott, W. P. and Foulk, P. W. “Layered implementations of persistent object stores”. Software Engineering Journal, March, 1989.Google Scholar
- 2.Cockshott, W. P., “Design of POMP — Persistent Object Management Coprocessor” Research report ARCH-1-88, University of Strathclyde Dept of Computer Science.Google Scholar
- 3.“i486 MICROPROCESSOR”, Intel, April 1989.Google Scholar
- 4.Keedy, J. L., “The MONADS-PC System: A Programmers Overview” Bericht Nr. 8/89, Universität Bremen InformatikGoogle Scholar
- 5.Tanenbaum, A., “Operating Systems, Design and Implementation” Prentice Hall, 1987Google Scholar