Abstract
In this paper we present the design and the realization of a system suitable to work as a fast prototyping platform for implementing several digital neural networks by means of FPGA each one with a different number of processing units and connectivity architecture. Thus we developed a system with a processing kernel working on neural algorithms in addition with a control unit and a communication unit that allow the managing and the interfacing both toward application field and a host computer for data downloading. To get the same performances varying the neural network implemented we developed a communication protocol that handle all the working operations. Its generality and adaptability at various working conditions allow an easy reconfiguration of the features of the neural network and therefore a saving in the time spent in testing and prototipation. Then we will show how a neural network can be implemented using up to four FPGA depending on its complexity. A case study will be presented to show the performances of the overall system.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
J. Cloutier, P. Y. Simard, “Hardware Implementation of the Backpropagation without Multiplication” in Proceedings of 4 th International Conference on Microelectronics for Neural Networks and Fuzzy Systems, Turin, Italy, September 26–281994, pp 46–55
G. Grossi, R. Posenato, M. Costa, D. Palmisano, E. Pasero, ”Fast Prototyping for Hardware Neural Networks”, in Proceedings of 5 th International Conference on Artificial Neural Networks ICANN 95, Paris, France, October 9–13 1995, vol. 1, pp. 411–416
Adaptive Solutions, ”CNAPS System Architecture Manual”, in Technical Manual, CNAPS Core Series, Adaptive Solutions Inc., 1400 N. W. Compton Drive, Suite 340, Beaverton, OR 97006, 1993
M. Costa, E. Filippi, E. Pasero, ”Relaxation of Hardware Requirements in Ensemble of Modular, non Degenerate Multy-Layer Perceptrons”, in Proceedings of 14 th IMACS World Congress, Atlanta, USA, July 1994, pp. 646–650
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1999 Springer-Verlag London Limited
About this paper
Cite this paper
Costa, M., Palmisano, D., Pasero, E., Ferassa, L.B., DiLello, A. (1999). A High Performances and High Versatility Reconfigurable System for Fast Prototyping of Digital Neural Network Based on FPGA. In: Marinaro, M., Tagliaferri, R. (eds) Neural Nets WIRN VIETRI-98. Perspectives in Neural Computing. Springer, London. https://doi.org/10.1007/978-1-4471-0811-5_32
Download citation
DOI: https://doi.org/10.1007/978-1-4471-0811-5_32
Publisher Name: Springer, London
Print ISBN: 978-1-4471-1208-2
Online ISBN: 978-1-4471-0811-5
eBook Packages: Springer Book Archive