Energy and Delay Models
This chapter introduces energy and delay metrics of digital circuits used to implement DSP algorithms. The discussion begins with energy and delay definitions for logic gates, including the analysis of various factors that contribute to energy consumption and propagation delay. Design tradeoffs with respect to tuning gate size, supply and threshold voltages are analyzed next, followed by setting up an energy-delay tradeoff analysis for use in circuit-level optimizations. The discussion of energy and delay metrics in this chapter aims to give DSP architecture designers an understanding of hardware cost for implementing their algorithms.
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- V. Stojanovi et al., "Energy-Delay Tradeoffs in Combinational Logic using Gate Sizing and Supply Voltage Optimization," in Proc. Eur. Solid-State Circuits Conf., Sept. 2002, pp. 211-214.Google Scholar