Energy and Delay Models

  • Dejan Marković
  • Robert W. Brodersen
Part of the Electrical Engineering Essentials book series (EEE)


This chapter introduces energy and delay metrics of digital circuits used to implement DSP algorithms. The discussion begins with energy and delay definitions for logic gates, including the analysis of various factors that contribute to energy consumption and propagation delay. Design tradeoffs with respect to tuning gate size, supply and threshold voltages are analyzed next, followed by setting up an energy-delay tradeoff analysis for use in circuit-level optimizations. The discussion of energy and delay metrics in this chapter aims to give DSP architecture designers an understanding of hardware cost for implementing their algorithms.


Supply Voltage Logic Gate Delay Model Leakage Energy Switching Energy 
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  1. Sakurai T, Newton AR (Apr. 1990) "Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas," IEEE J. Solid-State Circuits 25(2):584–594CrossRefGoogle Scholar
  2. V. Stojanovi et al., "Energy-Delay Tradeoffs in Combinational Logic using Gate Sizing and Supply Voltage Optimization," in Proc. Eur. Solid-State Circuits Conf., Sept. 2002, pp. 211-214.Google Scholar

Additional References

  1. Predictive Technology Models from ASU, [Online]. Available: Scholar
  2. J. Rabaey, A. Chandrakasan, and B. Nikolić, Digital Integrated Circuits: A Design Perspective, (2nd Ed), Prentice Hall, 2003.Google Scholar

Copyright information

© Springer Science+Business Media New York 2012

Authors and Affiliations

  • Dejan Marković
    • 1
  • Robert W. Brodersen
    • 2
  1. 1.Electrical Engineering DepartmentUniversity of California, Los AngelesLos AngelesUSA
  2. 2.Berkeley Wireless Research CenterUniversity of California, BerkeleyBerkeleyUSA

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