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An Energy-Efficient 3D Stacked STT-RAM Cache Architecture for CMPs

Chapter

Abstract

In this chapter, we introduce how to adopt spin-transfer torque random access memory (STT-RAM) as on-chip L2 caches to achieve better performance and lower energy consumption, compared to traditional L2 cache designs. STT-RAM is a promising memory technology for on-chip cache design because of its fast read access, high density, and non-volatility. Using 3D heterogeneous integrations, it becomes feasible and cost-efficient to stack STT-RAM atop conventional chip multiprocessors (CMPs). However, one disadvantage of STT-RAM is its long write latency and its high write energy. In this chapter, we first stack STT-RAM-based L2 caches directly atop CMPs and compare it against SRAM counterparts in terms of performance and energy. We observe that the direct STT-RAM stacking might harm the chip performance due to the aforementioned long write latency and high write energy. To solve this problem, we then propose two architectural techniques: read-preemptive write buffer and SRAM–STT-RAM hybrid L2 cache. The simulation result shows that our optimized STT-RAM L2 cache improves performance by 4.91 % and reduces power by 73.5 % compared to the conventional SRAM L2 cache with the similar area.

Keywords

Cache Line Data Migration Leakage Power NMOS Transistor Phase Change Memory 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  • Guangyu Sun
    • 1
  • Xiangyu Dong
    • 2
  • Yiran Chen
    • 3
  • Yuan Xie
    • 4
  1. 1.Peking UniversityBeijingChina
  2. 2.Qualcomm Research LabSan DiegoUSA
  3. 3.University of PittsburghPittsburghUSA
  4. 4.Pennsylvania State UniversityUniversity ParkUSA

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