Abstract
This chapter focuses on low-power and low-slew clock network design and analysis for through-silicon-via (TSV)-based three-dimensional stacked ICs (3D ICs). First, we study the impact of the TSV count and the TSV RC parasitics on clock power consumption. Several techniques are introduced to reduce the clock power consumption and slew of the 3D clock distribution network. We analyze how these design factors affect the overall wirelength, clock power, slew, and skew in 3D clock network design. Second, we study a two-step 3D clock tree synthesis method: (1) 3D abstract tree generation based on the three-dimensional method of means and medians (3D-MMM) algorithm; (2) buffering and embedding based on the slew-aware deferred-merge buffering and embedding (sDMBE) algorithm. We also extend the 3D-MMM method (3D-MMM-ext) to determine the optimal number of TSVs to be used in the 3D clock tree so that the overall power consumption is minimized. Related SPICE simulation indicates that: (1) a 3D clock network that uses multiple TSVs significantly reduces the clock power compared with the single-TSV case; (2) as the TSV capacitance increases, the power savings of a multiple-TSV clock network decreases; and (3) our 3D-MMM-ext method finds a close-to-optimal design point in the TSV count vs. power consumption tradeoff curve very efficiently.
The materials presented in this chapter are based on [27].
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Notes
- 1.
In this chapter, we use “TSV count” to refer to the total number of TSVs used in a 3D clock tree.
- 2.
In this chapter, wire segments denote the edges of the abstract tree, and are not uniformly distributed. Depending on the TSV insertion and buffer insertion on the abstract tree, a src-to-sink path usually contains tens of wire segments, with each segment length varies from tens of micro-meters to a few hundreds of micro-meters.
- 3.
Note that the TSV bound of infinity means that we do not impose any restriction on the maximum number of TSVs used in each die. This usually results in a high usage of TSVs that mainly targets at wirelength minimization.
References
C. Albrecht, A.B. Kahng, B. Liu, I.I. Mandoiu, A.Z. Zelikovsky, On the skew-bounded minimum-buffer routing tree problem. IEEE Trans. Comput. Aided Design Integr. Circuits Syst. 22(7), 937–945 (2003)
V. Arunachalam, W. Burleson, Low-power clock distribution in a multilayer core 3D microprocessor, in Proceedings of the 18th ACM Great Lakes Symposium on VLSI, Orlando, 2008, pp. 429–434
T. Bandyopadhyay, R. Chatterjee, D. Chung, M. Swaminathan, R. Tummala, Electrical modeling of through silicon and package vias, in IEEE International Conference on 3D System Integration, 2009. 3DIC 2009, San Francisco, pp. 1–8
K.D. Boese, A.B. Kahng, Zero-skew clock routing trees with minimum wirelength, in Proceedings of Fifth Annual IEEE International ASIC Conference and Exhibit, 1992, Rochester, 1992, pp. 17–21
W.C. Elmore, The transient analysis of damped linear networks with particular regard to wideband amplifiers. J. Appl. Phys. 19(1), 55–63 (1948)
E.G. Friedman, Clock distribution networks in synchronous digital integratedcircuits. Proc. IEEE 89(5), 665–692 (2001)
S. Hu, C.J. Alpert, J. Hu, S.K. Karandikar, Z. Li, W. Shi, C.N. Sze, Fast algorithms for slew-constrained minimum cost buffering. IEEE Trans. Comput. Aided Design Integr. Circuits Syst. 26(11), 2009–2022 (2007)
GSRC Benchmark, http://vlsicad.ucsd.edu/GSRC/bookshelf/Slots/BST
International technology roadmap for semiconductors (ITRS), http://www.itrs.net/
M. Jackson, A. Srinivasan, E. Kuh, Clock routing for high-performance ICs, in Proceedings of ACM Design Automation Conference, Orlando, 1990, pp. 573–579
G. Katti, M. Stucchi, K. De Meyer, W. Dehaene, Electrical modeling and characterization of through silicon via for three-dimensional ICs. Electron Devices IEEE Trans. 57(1), 256–262 (2010)
T.-Y. Kim, T. Kim, Clock tree embedding for 3D ICs, in Proceedings of Asia and South Pacific Design Automation Conference, Taipei, 2010, pp. 486–491
D.H. Kim, K. Athikulwongse, S.K. Lim, A study of through-silicon-via impact on the 3D stacked IC layout, in Proceedings IEEE International Conference on Computer-Aided Design, San Jose, 2009, pp. 674–680
J.U. Knickerbocker, P.S. Andry, B. Dang, R.R. Horton, M.J. Interrante, C.S. Patel, R.J. Polastre, K. Sakuma, R. Sirdeshmukh, E.J. Sprogis, S.M. Sri-Jayantha, A.M. Stephens, A.W. Topol, C.K. Tsang, B.C. Webb, S.L. Wright, Three-dimensional silicon integration. IBM J. Res. Dev. 52(6), 553–569 (2008)
J. Minz, X. Zhao, S.K. Lim, Buffered clock tree synthesis for 3D ICs under thermal variations, in Proceedings of Asia and South Pacific Design Automation Conference, Seoul, 2008, pp. 504–509
V.F. Pavlidis, I. Savidis, E.G. Friedman. Clock distribution networks for 3-D integrated circuits, in Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE, San Jose, 2008, pp. 651–654
Predictive Technology Model, http://ptm.asu.edu/
P.J. Restle, T.G. McNamara, D.A. Webber, P.J. Camporese, K.F. Eng, K.A. Jenkins, D.H. Allen, M.J. Rohn, M.P. Quaranta, D.W. Boerstler, C.J. Alpert, C.A. Carter, R.N. Bailey, J.G. Petrovick, B.L. Krauter, B.D. McCredie, A clock distribution network for microprocessors. IEEE J. Solid-State Circuits 36(5), 792–799 (2001)
I. Savidis, E.G. Friedman, Closed-form expressions of 3-D via resistance, inductance, and capacitance. IEEE Trans. Electron Devices 56(9), 1873–1881 (2009)
G.E. Tellez, M. Sarrafzadeh, Minimal buffer insertion in clock trees with skew and slew rate constraints. IEEE Trans. Comput. Aided Design Integr. Circuits Syst. 16(4), 333–342 (1997)
J. Vardaman, 3-D Through-silicon vias become a reality (2007). http://www.highbeam.com/doc/1G1-164627024.html
R. Weerasekera, M. Grange, D. Pamunuwa, H. Tenhunen, L.-R. Zheng, Compact modeling of through-silicon vias (TSVs) in three-dimensional (3-D) integrated circuits, in IEEE International Conference on 3D System Integration, 2009. 3DIC 2009, San Francisco, 2009, pp. 1–8
S.L. Wright, P.S. Andry, E. Sprogis, B. Dang, R.J. Polastre, Reliability testing of through-silicon vias for high-current 3D applications, in Proceedings of the 58th Electronic Components and Technology Conference, 2008. ECTC 2008, Orlando, 2008, pp. 879–883
J.-S. Yang, K. Athikulwongse, Y.-J. Lee, S.K. Lim, D.Z. Pan, TSV stress aware timing analysis with applications to 3D-IC layout optimization, in Proceedings of ACM Design Automation Conference, Anaheim, 2010, pp. 803–806
X. Zhao, S.K. Lim, Power and slew-aware clock network design for through-silicon-via (TSV) based 3D ICs, in Proceedings of Asia and South Pacific Design Automation Conference, Taipei, 2010, pp. 175–180
X. Zhao, D.L. Lewis, H.H.S. Lee, S.K. Lim, Pre-bond testable low-power clock tree design for 3D stacked ICs, in Proceedings of IEEE International Conference on Computer-Aided Design, San Jose, 2009, pp. 184–190
X. Zhao, J. Minz, S.K. Lim, Low-power and reliable clock network design for through silicon via based 3D ICs. IEEE Trans. Compon. Packag. Manuf. Technol. 1(2), 247–259 (2011)
Q.K. Zhu, High-Speed Clock Network Design (Springer, New York, 2003)
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Lim, S.K. (2013). Low Power Clock Routing for 3D IC. In: Design for High Performance, Low Power, and Reliable 3D Integrated Circuits. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-9542-1_4
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