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Impact of TSV Scaling on 3D IC Design Quality

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Abstract

TSVs incur two major kinds of overhead in the design of 3D ICs. First, TSVs lead to significant silicon area overhead. In addition, the non-negligible TSV parasitic capacitance causes delay overhead in 3D signal paths. Therefore, the possibility of obtaining all the benefits such as wirelength reduction and better performance from 3D ICs is highly dependent on TSV size and TSV capacitance. Meanwhile, TSVs are getting smaller to minimize their negative effects and sub-micron TSVs are expected to be fabricated in the near future. At the same time, the device size is also being downscaled beyond 32 and 22 nm, so it is highly likely that future 3D ICs are built with sub-micron TSVs and advanced device technologies. In this chapter, we study the impact of sub-micron TSVs on the quality of today and future 3D ICs. For future process technologies, we develop 22 and 16 nm libraries. Using these future process libraries as well as a 45 nm library, we generate 3D IC layouts with different TSV sizes and capacitances and study the impact of sub-micron TSVs thoroughly.

The materials presented in this chapter are based on [7].

Keywords

  • Area Overhead
  • Benchmark Circuit
  • Footprint Area
  • Critical Path Delay
  • Dynamic Power Consumption

These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Notes

  1. 1.

    If we assume that only the TSV size and the TSV height are downscaled while other design parameters such as the liner thickness and doping concentration are fixed, TSV capacitance decreases as TSVs are downscaled.

  2. 2.

    This observation is strongly dependent on TSV capacitance used at each process node.

  3. 3.

    A “X μm TSV” in this chapter denotes a TSV whose width ( = for square-shaped TSVs) or diameter ( = for cylindrical-type TSVs) is X μm.

  4. 4.

    We referred to the standard cell layouts of the Nangate 45 nm standard cell library [18].

  5. 5.

    There exist many kinds of 3D integration and some of them (e.g., core-DRAM stacking) provide a huge amount of power saving by removing long chip-to-chip connections.

  6. 6.

    Note that this is a simplified analysis. In reality, the total power should be computed in a more sophisticated fashion taking switching activities of nets and gates into account.

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Lim, S.K. (2013). Impact of TSV Scaling on 3D IC Design Quality. In: Design for High Performance, Low Power, and Reliable 3D Integrated Circuits. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-9542-1_19

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  • DOI: https://doi.org/10.1007/978-1-4419-9542-1_19

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