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3D IC Cooling with Micro-Fluidic Channels

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Design for High Performance, Low Power, and Reliable 3D Integrated Circuits

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Abstract

Heat removal and power delivery have become two major reliability concerns in 3D IC technology. To alleviate thermal problem, two possible solutions have been proposed: thermal-through-silicon-vias (T-TSVs) and micro-fluidic channel (MFC) based cooling. In case of power delivery, a complex power distribution network is required to deliver currents reliably to all parts of the 3D IC while suppressing the power supply noise to an acceptable level. However, these thermal and power networks pose major challenges in signal routability and congestion. This is because signal, power, and thermal interconnects are all competing for routing space, and the related TSVs interfere with gates and wires in each die. In this chapter we study a co-optimization methodology for signal, power, and thermal interconnects in 3D ICs based on design of experiments (DOE) and response surface methodology (RSM). The goal of our holistic approach is to improve signal, thermal, and power noise metrics and to provide fast and accurate design space exploration for early design stage. We also provide an in-depth comparison between T-TSV vs. MFC based cooling method and discuss how to employ DOE and RSM techniques to co-optimize the interconnects. Our DOE-based optimization found the optimal design point with less effort than a gradient search based optimization.

The materials presented in this chapter are based on [16].

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References

  1. M. Bakir, B. Dang, J. Meindl, Revolutionary nanosilicon ancillary technologies for ultimate-performance gigascale systems, in Proceedings of the IEEE Custom Integrated Circuits Conference, San Jose, 2007, pp. 421–428

    Google Scholar 

  2. G. Box, D. Behnken, Some new three level designs for the study of quantitative variables. Technometrics 2, 455–475 (1960)

    Article  MathSciNet  Google Scholar 

  3. F. Brglez, R. Drechsler, Design of experiments in CAD: context and new data sets for ISCAS’99. Proc. IEEE Int. Symp. Circuit Syst. 6, 424–427 (1999)

    Google Scholar 

  4. J. Cong, S.K. Lim, Edge separability based circuit clustering with application to circuit partitioning, in Proceedings of the Asia and South Pacific Design Automation Conference, Yokohama, 2000, pp. 429–434.

    Google Scholar 

  5. J. Cong, Y. Zhang, Thermal-driven multilevel routing for 3-D ICs, in Proceedings of the Asia and South Pacific Design Automation Conference, Shanghai, vol. 1, 2005, pp. 121–126

    Google Scholar 

  6. B. Dang, M.S. Bakir, J.D. Meindl, Integrated thermal-fluidic I/O interconnect for an on-chip microchannel heat sink. IEEE Electron Device Lett. 27(2), 117–119 (2006)

    Article  Google Scholar 

  7. G. Derringer, R. Suich, Simultaneous optimization of several response variables. J. Qual. Technol. 12(4), 214–219 (1980)

    Google Scholar 

  8. R.A. Fisher, The Design of Experiments (Oliver and Boyd, London, 1935)

    Google Scholar 

  9. B. Goplen, S. Sapatnekar, Thermal via placement in 3D ICs, in Proceedings of the International Symposium on Physical Design, San Francisco, 2005, pp. 167–174

    Google Scholar 

  10. C.-W. Ho, A.E. Ruehli, P.A. Brennan, The modified nodal approach to network analysis. IEEE Trans. Circuit Syst. 22(6), 504–509 (1975)

    Article  Google Scholar 

  11. G. Huang et al., Compact physical models for power supply noise and chip/package co-design of gigascale integration, in Proceedings of IEEE Electronic Components and Technology Conference, Reno, 2007, pp. 1659–1666.

    Google Scholar 

  12. A.J. Joseph et al., Through-silicon vias enable next-generation SiGe power amplifiers for wireless communications. IBM J. Res. Dev. 52(6), 635–648 (2008)

    Article  Google Scholar 

  13. D.H. Kim, K. Athikulwongse, S.K. Lim, A study of through-silicon-via impact on the 3D stacked IC layout, in Proceedings of the IEEE International Conference on Computer-Aided Design, San Jose, 2009, pp. 674–680

    Google Scholar 

  14. Y.J. Kim, Y.K. Joshi, A.G. Fedorov, Y.-J. Lee, S.-K. Lim, Thermal characterization of interlayer microfluidic cooling of three-dimensional integrated circuits with nonuniform heat flux. J. Heat Transf. 132(4), 214–219 (2010)

    Article  Google Scholar 

  15. J.-M. Koo, S. Im, L. Jiang, K.E. Goodson, Integrated microchannel cooling for three-dimensilonal electronic architecture. J. Heat Transf. 127, 49–58 (2005)

    Article  Google Scholar 

  16. Y.-J. Lee, S.K. Lim, Co-optimization and analysis of signal, power, and thermal interconnects in 3D ICs, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Syst. 30(11), 1635–1648 (2011)

    Google Scholar 

  17. R.L. Mason, R.F. Gunst, J.L. Hess, Statistical Design and Analysis of Experiments With Applications to Engineering and Science, 2nd edn. (Wiley, New York, 2003)

    MATH  Google Scholar 

  18. R.H. Myers, D.C. Montgomery. Response Surface Methodology: Process and Product Optimization Using Designed Experiments (Wiley, New York, 1995)

    MATH  Google Scholar 

  19. V. Nookala, Y. Chen, D.J. Lilja, S.S. Sapatnekar, Microarchitecture-aware floorplanning using a statistical design of experiments approach, in Proceedings of the ACM Design Automation Conference, Anaheim, 2005, pp. 579–584.

    Google Scholar 

  20. North Carolina State University, NCSU FreePDK, available online at http://www.eda.ncsu.edu/wiki/FreePDK

  21. S.V. Patankar, Numerical Heat Transfer and Fluid Flow (Hemisphere, Washington, DC, 1980).

    MATH  Google Scholar 

  22. M. Pathak, S.K. Lim, Thermal-aware Steiner Routing for 3D Stacked ICs, in Proceedings of the IEEE International Conference on Computer-Aided Design, San Jose, 2007, pp. 205–211

    Google Scholar 

  23. M. Pathak, Y.-J. Lee, T. Moon, S.K. Lim, Through silicon via management during 3D physical design: when to add and how many? in Proceedings of the IEEE International Conference on Computer-Aided Design, San Jose, 2010, pp. 387–394

    Google Scholar 

  24. D. Sekar et al., A 3D-IC technology with integrated microchannel cooling, in Proceedings of the International Interconnect Technology Conference, Burlingame, 2008

    Google Scholar 

  25. D.B. Tuckerman, R.F.W. Pease, High-performance heat sinking for VLSI. IEEE Electron Device Lett. 2, 126–129 (1981)

    Article  Google Scholar 

  26. E. Wong, S. Lim, 3D floorplanning with thermal vias, in Proceedings of the Design, Automation and Test in Europe, Münich, vol. 1, 2006, pp. 1–6

    Google Scholar 

  27. Q. Zhang et al., Development of robust interconnect model based on design of experiments and multiobjective optimization. IEEE Trans. Electron Device 48(9), 1885–1891 (2001)

    Article  Google Scholar 

  28. T. Zhang, Y. Zhan, S.S. Sapatnekar, Temperature-aware routing in 3D ICs, in Proceedings of the Asia and South Pacific Design Automation Conference, Yokohama, 2006, pp. 309–314

    Google Scholar 

  29. Q. Zhou, K. Sun, K. Mohanram, D.C. Sorensen, Large power grid analysis using domain decomposition, in Proceedings of the Design, Automation and Test in Europe, Münich, 2006, pp. 1–6

    Google Scholar 

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  1. School of Electrical and Computer Engineering, Georgia Institute of Technology, 777 Atlantic Drive NW, Atlanta, Georgia, USA

    Sung Kyu Lim

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  1. Sung Kyu Lim
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Lim, S.K. (2013). 3D IC Cooling with Micro-Fluidic Channels. In: Design for High Performance, Low Power, and Reliable 3D Integrated Circuits. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-9542-1_12

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  • DOI: https://doi.org/10.1007/978-1-4419-9542-1_12

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  • Online ISBN: 978-1-4419-9542-1

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