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Multi-objective Architectural Floorplanning for 3D IC

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Design for High Performance, Low Power, and Reliable 3D Integrated Circuits

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Abstract

In this chapter, we study the multi-objective micro-architectural floorplanning algorithm for high performance processors implemented in IC. Our floorplanner takes a micro-architectural netlist and determines the dimension as well as the placement of the functional modules into single or multiple device layers while simultaneously achieving high performance and thermal reliability. The traditional design objectives such as area and wirelength are also considered. Our 3D floorplanning algorithm considers the following 3D-specific issues: vertical overlap optimization and bonding-aware layer partitioning. Our hybrid floorplanning approach combines Linear Programming and Simulated Annealing, which is shown to be very effective in obtaining high-quality solutions in short runtime under the multi-objective goals. We provide comprehensive experimental results on making tradeoffs among performance, thermal, area, and wirelength for 3D ICs.

The materials presented in this chapter are based on [25].

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Notes

  1. 1.

    Our algorithm is general enough to take in many different configurations. For the sake of expediency, one configuration was chosen for experimentation.

  2. 2.

    The average number of iterations needed was found to be approximately seven for the largest number of layers. A smaller number of layers requires fewer iterations.

  3. 3.

    Since we add performance and thermal-related weights to the pure wirelength, we do not explicitly consider non-weighted pure wirelength objective. However, we report the wirelength metric in all of our experiments to show the impact of this multi-objective on wirelength.

  4. 4.

    Note that the area objective is used in all of these variations. The area objective has a positive impact on performance and wirelength objectives and a negative impact on thermal objective.

  5. 5.

    Note that it is possible to impose the vertical overlap constraints among the related groups of modules. The investigation of this direction is out of the scope of this chapter, which may require the extension of floorplanning encoding scheme such as Sequence Pair [38].

  6. 6.

    We use the lower left corner of each module in our case.

  7. 7.

    Our recent study [42] shows that Random Walk method can improve the runtime of thermal simulation significantly. Our future work includes the integration of this scheme in our micro-architectural floorplanning.

  8. 8.

    These floorplans also highlight the challenge in area optimization for multi-objective, multi-layer floorplanning problem. Our future work tries to address this problem more effectively. A possible solution is to utilize the whitespace for decoupling capacitors, thermal vias, buffers, etc.

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  1. School of Electrical and Computer Engineering, Georgia Institute of Technology, 777 Atlantic Drive NW, Atlanta, Georgia, USA

    Sung Kyu Lim

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Lim, S.K. (2013). Multi-objective Architectural Floorplanning for 3D IC. In: Design for High Performance, Low Power, and Reliable 3D Integrated Circuits. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-9542-1_10

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  • DOI: https://doi.org/10.1007/978-1-4419-9542-1_10

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