Skip to main content
SpringerLink
Log in

Regular Versus Irregular TSV Placement for 3D IC

  • Chapter
  • First Online:
Design for High Performance, Low Power, and Reliable 3D Integrated Circuits

Abstract

Through-silicon via (TSV) is the enabling technology for fine-grained integration of multiple dies into a single 3D stack. However, TSVs occupy significant silicon area due to their sheer size, which has a great effect on the power and performance of 3D ICs. Whereas well-managed TSVs alleviate routing congestion, reduce wirelength, and improve performance, excessive or ill-managed TSVs not only increase the die area but also degrade performance and power. In this chapter, we study the impact of TSVs on the quality of 3D IC layouts. We first study two design schemes, namely TSV co-placement (irregular TSV placement) and TSV site (regular TSV placement), for the design of 3D ICs. In addition, we develop a force-directed 3D gate-level placement algorithm to find optimal locations of TSVs and gates. One key problem to solve in regular TSV placement is how to assign 3D nets to pre-placed TSVs. To solve this problem effectively, we study two TSV assignment algorithms, compare them with other TSV assignment algorithms, and analyze the impact of the quality of TSV assignment algorithms on 3D ICs. Experimental results show that the wirelength of 3D ICs is shorter than that of 2D ICs by up to 25 %. We also compare timing and power of 2D and 3D ICs.

The materials presented in this chapter are based on [19].

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 89.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 119.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Notes

  1. 1.

    We use diameter and width for cylindrical-shaped TSVs and square-shaped TSVs, respectively.

  2. 2.

    The area overhead caused by a TSV is due to the TSV, liner around the TSV, and keep-out zone. In our work, A TSV of a 1 ×TSV is 6.1009 μm2.

  3. 3.

    If we want to apply our design methodology to via-last type TSVs, we need additional steps. For the TSV co-placement flow, we need to avoid overlaps between two TSVs in adjacent dies. This can be resolved by applying another force between two TSVs in adjacent dies or by legalizing TSV locations after global placement. For the TSV-site flow, we can avoid overlaps between two TSVs in adjacent dies by using different TSV array size. If re-distribution layers exist, however, our design methodology can be directly applied to via-last type TSVs.

  4. 4.

    When the number of dies increases, if we ignore TSV area, the footprint area monotonically decreases. However, the number of TSVs has a great effect on the footprint area. If too many TSVs are used at a particular partitioning, the footprint area at that die count could increase.

  5. 5.

    The TSV capacitance used in [21] is 37 fF for a square-shaped TSV whose width and height are 5 and 50 μm, respectively. In our case, TSV width is 1.50 μm and TSV height is 20 μm, so we actually obtain 4.43 fF for our TSV capacitance by linear scaling because TSV capacitance is almost linearly proportional to TSV width and TSV height [28].

References

  1. K. Bernstein, P. Andry, J. Cann, P. Emma, D. Greenberg, W. Haensch, M. Ignatowski, S. Koester, J. Magerlein, R. Puri, A. Young, Interconnects in the third dimension: design challenges for 3D ICs, in Proceedings of ACM Design Automation Conference (IEEE, Piscataway, 2007), pp. 562–567

    Google Scholar 

  2. E. Beyne, P.D. Moor, W. Ruythooren, R. Labie, A. Jourdain, H. Tilmans, D.S. Tezcan, P. Soussan, B. Swinnen, R. Cartuyvels, Through-silicon via and die stacking technologies for microsystems-integration, in Proceedings of IEEE International Electron Devices Meeting (IEEE, Piscataway, 2008), pp. 1–4

    Google Scholar 

  3. Cadence Design Systems, QRC Extraction Users Manual 8.1.2

    Google Scholar 

  4. Cadence Design Systems, Soc Encounter, 2009. http://www.cadence.com

  5. H. Chaabouni, M. Rousseau, P. Leduc, A. Farcy, R.E. Farhane, A. Thuaire, G. Haury, A. Valentian, G. Billiot, M. Assous, F.D. Crecy, J. Cluzel, A. Toffoli, D. Bouchu, L. Cadix, T. Lacrevaz, P. Ancey, N. Sillon, B. Flechet, Investigation on TSV impact on 65 nm CMOS devices and circuits, in Proceedings of IEEE International Electron Devices Meeting (IEEE, Piscataway, 2010)

    Google Scholar 

  6. J. Cong, S.K. Lim, Edge separability based circuit clustering with application to multi-level circuit partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(3), 346–357 (2004)

    Article  Google Scholar 

  7. J. Cong, G. Luo, A Multilevel analytical placement for 3D ICs, in Proceedings of Asia and South Pacific Design Automation Conference (IEEE, Piscataway, 2009)

    Google Scholar 

  8. J. Cong, G. Luo, J. Wei, Y. Zhang, Thermal-aware 3D IC placement via transformation, in Proceedings of Asia and South Pacific Design Automation Conference (IEEE, Piscataway, 2007), pp. 780–785

    Google Scholar 

  9. X. Dong, Y. Xie, System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs), in Proceedings of Asia and South Pacific Design Automation Conference (IEEE, Piscataway, 2009), pp. 234–241

    Google Scholar 

  10. B. Goplen, S. Sapatnekar, Efficient thermal placement of standard cells in 3D ICs using a force directed approach, in Proceedings of IEEE International Conference on Computer-Aided Design (ACM, New York; IEEE, Piscataway, 2003)

    Google Scholar 

  11. B. Goplen, S. Sapatnekar, Thermal via placement in 3D ICs, in Proceedings of International Symposium on Physical Design (ACM, New York, 2005), pp. 167–174

    Google Scholar 

  12. B. Goplen, S. Sapatnekar, Placement of 3D ICs with thermal and interlayer via considerations, in Proceedings of ACM Design Automation Conference (IEEE, Piscataway, 2007), pp. 626–631

    Google Scholar 

  13. H. Hua, C. Mineo, K. Schoenfliess, A. Sule, S. Melamed, R. Jenkal, W.R. Davis, Exploring compromises among timing, power and temperature in three-dimensional integrated circuits, in Proceedings of ACM Design Automation Conference (IEEE, Piscataway, 2006), pp. 997–1002

    Google Scholar 

  14. IMEC, 3D stacked IC (3D-SIC), 2008. http://www.imec.be

  15. IWLS, IWLS 2005 benchmarks, 2005. http://www.iwls.org/iwls2005

  16. J.W. Joyner, P. Zarkesh-Ha, J.A. Davis, J.D. Meindl, A three-dimensional stochastic wire-length distribution for variable separation of strata, in Proceedings of IEEE International Interconnect Technology Conference (IEEE, Piscataway, 2000), pp. 126–128

    Google Scholar 

  17. G. Karypis, V. Kumar, hMETIS, a hypergraph partitioning package version 1.5.3, 2007. http://glaros.dtc.umn.edu/gkhome/metis/hmetis/download

  18. D.H. Kim, S.K. Lim, Through-silicon-via-aware delay and power prediction model for buffered interconnects in 3D ICs, in Proceedings of ACM/IEEE International Workshop on System Level Interconnect Prediction (ACM, New York, 2010), pp. 25–32

    Google Scholar 

  19. D.H. Kim, K. Athikulwongse, S.K. Lim, A study of through-silicon-via impact on the 3D stacked IC layout, in Proceedings of IEEE International Conference on Computer-Aided Design (ACM, New York, 2009)

    Google Scholar 

  20. D.H. Kim, S. Mukhopadhyay, S.K. Lim, Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs, in Proceedings of ACM/IEEE International Workshop on System Level Interconnect Prediction (ACM, New York, 2009), pp. 85–92

    Google Scholar 

  21. D.H. Kim, S. Mukhopadhyay, S.K. Lim, TSV-aware interconnect length and power prediction for 3D stacked ICs, in Proceedings of IEEE International Interconnect Technology Conference (IEEE, Piscataway, 2009), pp. 26–28

    Google Scholar 

  22. M. Koyanagi, T. Fukushima, T. Tanaka, High-deisnty through silicon vias for 3-D LSIs, in Proceedings of the IEEE (IEEE, Piscataway 2009), pp. 49–59

    Google Scholar 

  23. H.W. Kuhn. The hungarian method for the assignment problem. Nav. Res. Logist. 2, 83–97 (1955)

    Article  Google Scholar 

  24. Y.-J. Lee, S.K. Lim, Timing analysis and optimization for 3D stacked multi-core microprocessors, in Proceedings of International 3D System Integration Conference (IEEE, Piscataway, 2010)

    Google Scholar 

  25. H.Y. Li, E. Liao, X.F. Pang, H. Yu, X.X. Yu, J.Y. Sun, Fast electroplating TSV process development for the via-last approach, in IEEE Electronic Components and Technology Conference (IEEE, Piscataway, 2010), pp. 777–780

    Google Scholar 

  26. Nangate, Nangate 45 nm open cell library, 2009. http://www.nangate.com

  27. NCSU, FreePDK45, 2009. http://www.eda.ncsu.edu/wiki/FreePDK

  28. I. Savidis, E.G. Friedman, Closed-form expressions of 3-D via resistance, inductance, and capacitance. IEEE Trans. Electron Devices 56(9), 1873–1881 (2009)

    Article  Google Scholar 

  29. P. Spindler, U. Schlichtmann, F.M. Johannes, Kraftwerk2 – a fast force-directed quadratic placement approach using an accurate net model. IEEE Trans Comput. Aided Des. Integr. Circuits Syst. 27(8), 1398–1411 (2008)

    Article  Google Scholar 

  30. Synopsys, PrimeTime, 2008. http://www.synopsys.com

  31. T. Thorolfsson, K. Gonsalves, P.D. Franzon, Design automation for a 3DIC FFT processor for synthetic aperture radar: a case study, in Proceedings of ACM Design Automation Conference (ACM, New York, 2009), pp. 51–56

    Google Scholar 

  32. M.-C. Tsai, T.-C. Wang, T. Hwang, Through-silicon via planning in 3-D floorplanning, in IEEE Transactions on VLSI Systems (IEEE, New York, 2010)

    Google Scholar 

  33. H. Yan, Z. Li, Q. Zhou, X. Hong, Via assignment algorithm for hierarchical 3-D placement, in Proceedings of IEEE International Conference on Communications, Circuits and Systems (IEEE, Piscataway, 2005), pp. 1225–1229

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. School of Electrical and Computer Engineering, Georgia Institute of Technology, 777 Atlantic Drive NW, Atlanta, Georgia, USA

    Sung Kyu Lim

Authors
  1. Sung Kyu Lim
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

Copyright information

© 2013 Springer Science+Business Media New York

About this chapter

Cite this chapter

Lim, S.K. (2013). Regular Versus Irregular TSV Placement for 3D IC. In: Design for High Performance, Low Power, and Reliable 3D Integrated Circuits. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-9542-1_1

Download citation

  • DOI: https://doi.org/10.1007/978-1-4419-9542-1_1

  • Published:

  • Publisher Name: Springer, New York, NY

  • Print ISBN: 978-1-4419-9541-4

  • Online ISBN: 978-1-4419-9542-1

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation