General Considerations of High-/Mixed-VDD Analog and RF Circuits and Systems

  • Pui-In Mak
  • Rui Paulo Martins
Part of the Analog Circuits and Signal Processing book series (ACSP)


Instead of just following the rapid downsizing of V DD mixed-voltag/mixed-voltage RF and analog CMOS circuits and systems have emerged as a prospective alternative [1], to deal with the wireless technology trends such as software-defined radio and cognitive radio; both are hungry for bandwidth and dynamic range. An elevated V DD, or a hybrid use of I/O and core V DD’s, in conjunction with optimum selection of thin- and thick-oxide MOSFETS open up much new design possibilities in re-defining circuit topologies, while maintaining most speed and area benefits of advanced fine linewidth processes [2]. Voltage-conscious bias techniques and overdrive protection circuits are simple and low overhead techniques to ensure the reliability of all devices. This chapter studies the basic design concept, system design considerations and some state-of-the-art circuit examples. A wide variety of analog and RF CMOS circuits featuring high-/mixed-V DD is discussed. Those circuits comprise power amplifier, low-noise amplifier, mixer, operational-amplifier-based analog circuits, sample-and-hold amplifier and line driver. Reliability metrics such as oxide breakdown voltage, hot carrier injection (HCI), time dependent dielectric breakdown (TDDB), and bias temperature instability (BTI) will be briefly addressed. The involved concepts and techniques are generally extendable to different wireless and non-wireless applications.


Line Driver Negative Bias Temperature Instability Overdrive Voltage Cascode Transistor Recycling Fold Cascode 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 1.
    A.-J. Annema, B. Nauta, R. V. Langevelde and H. Tuinhout, “Analog Circuits in Ultra-Deep-Submicron CMOS,” IEEE J. Solid-State Circuits (JSSC), vol. 40, pp. 132–143, Jan., 2005.CrossRefGoogle Scholar
  2. 2.
    J. Borremans, G. Mandal, V. Giannini, T. Sano, M Ingels, B. Verbruggenn and J. Craninckx “A 40nm CMOS Highly Linear 0.4-to-6GHz Receiver Resilient to 0dBm Out-of-Band Blockers,” ISSCC Dig. Tech. Papers, pp. 62–63, Feb. 2011.Google Scholar
  3. 3.
    STMicroelectronics technology profile in Circuits Multi-Projet (R) [Online]:
  4. 4.
    P.-I. Mak, S.-P. U and R. P. Martins, “Transceiver Architecture Selection – Review, State-of-the-Art Survey and Case Study,” IEEE Circuits and Systems Magazine, Issue 2, pp. 6–25, Jun. 2007.Google Scholar
  5. 5.
    B. Serneels and M. Steyaert, Design of High voltage xDSL Line Drivers in Standard CMOS, Springer, 2008.Google Scholar
  6. 6.
    M. Zargari, L. Nathawad, H. Samavati, et al., “A Dual-Band CMOS MIMO Radio SoC for IEEE 802.11n Wireless LAN,” IEEE J. Solid-State Circuits (JSSC), vol. 43, pp. 2882–2895, Dec., 2008.CrossRefGoogle Scholar
  7. 7.
    R. Bagheri, A. Mirzaei, S. Chehrazi, M. E. Heidari, M. Lee, M. Mikhemar, W. Tang, and A. A. Abidi, “An 800-MHz–6-GHz software-defined wireless receiver in 90-nm CMOS,” IEEE J. Solid-State Circuits (JSSC), vol. 41, no. 12, pp. 2860–2876, Dec. 2006.CrossRefGoogle Scholar
  8. 8.
    C. Andrews, A. Molnar, “A Passive-Mixer-First Receiver with Baseband-Controlled RF Impedance Matching, <6dB NF, and > 27dBm Wideband IIP3,” ISSCC Dig. Tech. Papers, pp. 46–47, Feb. 2010.Google Scholar
  9. 9.
    H. Moon, S. Lee, S-C. Heo, H. Yu, J. Yu, J-S. Chang, S-I. Choi, B-H. Park, “A 23mW Fully Integrated GPS Receiver with Robust Interferer Rejection in 65nm CMOS,” ISSCC Dig. Tech. Papers, pp. 68–69, Feb. 2010.Google Scholar
  10. 10.
    L. Miao, P.-I. Mak, Z. Yan and R. P. Martins, “A High-Voltage-Enabled Recycling Folded Cascode OpAmp for Nanoscale CMOS Technologies,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 33–36, May 2011.Google Scholar
  11. 11.
    R. S. Assaad, J. S. Martinez, “The Recycling Folded Cascode: A General Enhancement of the Folded Cascode Amplifier,” IEEE J. Solid-State Circuits, vol. 44, no. 9, Sep. 2009.Google Scholar
  12. 12.
    K. Ishida, A. Tamtrakarn and T. Sakurai, “An Outside-Rail Opamp Design Targeting for Future Scaled Transistors,” IEEE Asian Solid-State Circuits Conference (A-SSCC), pp.73–76, Nov. 2005.Google Scholar
  13. 13.
    B. Serneels, M. Steyaert and W. Dehaene, “A 237 mW aDSL2+ CO Line Driver in a Standard 1.2V 130nm CMOS Technology,” ISSCC Dig. Tech. Papers, pp. 524–525, Feb. 2007.Google Scholar
  14. 14.
    S.-M. Yoo. J.S. Walling, E. C. Woo and D.J. Allstot, “A Switched-Capacitor Power Amplifier for EER/Polar Transmitters,” ISSCC Dig. Tech. Papers, pp.428–430, Feb. 2011.Google Scholar
  15. 15.
    H. Xu, Y. Palaskas, A. Ravi, M. Sajadieh, M. A. El-Tanani and K. Soumyanath, “A Flip-Chip-Packaged 25.3 dBm Class-D Outphasing Power Amplifier in 32 nm CMOS for WLAN Application,” IEEE J. Solid-State Circuits (JSSC), vol. 46, no. 7, pp. 1596–1605, Jul. 2011.CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media New York 2012

Authors and Affiliations

  • Pui-In Mak
    • 1
  • Rui Paulo Martins
    • 1
  1. 1.University of MacauMacaoChina

Personalised recommendations