Skip to main content

Bidirectional Noc Architecture

  • Chapter
  • First Online:
Reconfigurable Networks-on-Chip
  • 918 Accesses

Abstract

A Bidirectional channel Network-on-Chip (BiNoC) architecture is proposed in this chapter to enhance the performance of on-chip communication. In a BiNoC, each communication channel allows itself to be dynamically reconfigured to transmit flits in either direction.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 139.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. S. Kumar, A. Jantsch, J. P. Soininen, M. Forsell, M. Millberg, J. Oberg, K. Tiensyrja, and A. Hemani, “A Network-on-Chip Architecture and Design Methodology,” in Proceedings of the International Symposium on Very Large Scale Integration, pp. 105-112, April 2000

    Google Scholar 

  2. R. Marculescu, U. Y. Ogras, L. S. Peh, N. E. Jerger, and Y. Hoskote, “Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 1, pp. 3-21, January 2009

    Google Scholar 

  3. T. Bjerregaard and S. Mahadevan, “A Survey of Research and Practices of Network-on-Chip,” ACM Computing Surveys, vol. 38, no. 1, pp. 1-51, March 2006

    Google Scholar 

  4. D. Bertozzi, A. Jalabert, M. Srinivasan, R. Tamhankar, S. Sterqiou, L. Benini, and G. DeMicheli, “NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-chip,” IEEE Transactions on Parallel and Distributed Systems, vol. 16, no. 2, pp. 113-129, February 2005

    Google Scholar 

  5. U. Orgas, J. Hu, and R. Marculescu, “Key Research Problems in NoC Design: A Holistic Perspective,” in Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, pp 69-74, September 2005

    Google Scholar 

  6. H. G. Lee, N. Chang, U. Y. Ogras, and R. Marculescu, “On-Chip Communication Architecture Exploration: A Quantitative Evaluation of Point-to-Point, Bus and Network-on-Chip Approaches,” ACM Transactions on Design Automation of Electronic Systems, vol. 12, no. 3, pp. 1-20, August 2007

    Google Scholar 

  7. J. D. Owens, W. J. Dally, R. Ho, D. N. Jayasimha, S. W. Keckler, and L. S. Peh, “Research Challenges for On Chip Interconnection Networks,” IEEE Micro, vol. 27, no. 5, pp. 96-108, November 2007

    Google Scholar 

  8. J. Lillis and C. Cheng, “Timing Optimization for Multisource Nets: Characterization and Optimal Repeater Insertion,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 3, pp. 322-331, Mar. 1999

    Google Scholar 

  9. S. Bobba and I. N. Hajj, “High-Performance Bidirectional Repeaters,” in Proceedings of the Great Lakes Symposium on Very Large Scale Integration, pp. 53-58, March 2000

    Google Scholar 

  10. A. Nalamalpu, S. Srinivasan, and W. P. Burleson, “Boosters for Driving Long Onchip Interconnects – Design Issues, Interconnect Synthesis, and Comparison with Repeaters,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 1, pp. 50-62, January 2002

    Google Scholar 

  11. H. Ito, M. Kimura, K. Miyashita, T. Ishii, K. Okada, and K. Masu, “A Bidirectional- and Multi-Drop-Transmission-Line Interconnect for Multipoint-to-Multipoint On-Chip Communications,” IEEE Journal of Solid-State Circuits, vol. 43, no. 4, pp. 1020-1029, April 2008

    Google Scholar 

  12. M. A. A. Faruque, T. Ebi, and J. Henkel, “Configurable Links for Runtime Adaptive On-Chip Communication,” in Proceedings of the Design Automation and Test in Europe Conference, pp. 256-261, April 2009

    Google Scholar 

  13. M. H. Cho, M. Lis, K. S. Shim, M. Kinsy, T. Wen, and S. Devadas, “Oblivious Routing in On-Chip Bandwidth-Adaptive Networks,” in Proceedings of the Parallel Architectures and Compilation Techniques, pp. 181-190, September 2009

    Google Scholar 

  14. Y. C. Lan, S. H. Lo, Y. C. Lin, Y. H. Hu, and S. J. Chen, “BiNoC: A Bidirectional NoC Architecture with Dynamic Self-Reconfigurable Channel,” in Proceedings of the International Symposium on Network-on-Chip, pp. 266-275, May 2009

    Google Scholar 

  15. L. S. Peh and W. J. Dally, “A Delay Model and Speculative Architecture for Pipelined Routers,” in Proceedings of the International Symposium on High-Performance Computer Architecture, pp. 255-266, January 2001

    Google Scholar 

  16. W. J. Dally and B. Towles, Principles and Practices of Interconnection Networks, Morgan Kaufmann, 2004

    Google Scholar 

  17. J. D. Owens, W. J. Dally, R. Ho, D. N. Jayasimha, S. W. Keckler, and L. S. Peh, “Research Challenges for On Chip Interconnection Networks,” IEEE Micro, vol. 27, no. 5, pp. 96-108, Nov. 2007

    Google Scholar 

  18. D. A. Menasce and R. R. Muntz, “Locking and Deadlock Detection in Distributed Data Base,” IEEE Transactions on Software Engineering, vol. SE-5, no. 3, pp. 195-202, May 1979

    Google Scholar 

  19. M. Lis, M. H. Cho, K. S. Shim, and S. Devadas, “Path-Diverse In-Order Routing,” in Proceedings of the International Conference on Green Circuits and Systems, pp. 311-316, June 2010

    Google Scholar 

  20. S. Murali, D. Atienza, L. Benini, and G. DeMicheli, “A Multi-Path Routing Strategy with Guaranteed In-Order Packet Delivery and Fault-Tolerance for Network-on-Chip,” in Proceedings of the Design Automation Conference, pp. 845-848, July 2006

    Google Scholar 

  21. M. Lis, K. S. Shim, M. H. Cho, and S. Devadas, “Guaranteed In-Order Packet Delivery using Exclusive Dynamic Virtual-channel Allocation,” Massachusetts Institute of Technology, Technical Report, CSAIR-TR-2009-036, August 2009

    Google Scholar 

  22. D. C. Gazis, Traffic Science, John Wiley and Sons, 1974

    Google Scholar 

  23. R. Dick, “Embedded System Synthesis Benchmark Suites (E3S),” http://ziyang.eecs.umich.edu/~dickrp/e3s/, Accessed January 2011

  24. M. Zhang and C. S. Choy, “Low-Cost VC Allocator Design for Virtual-channel Wormhole Routers in Network-on-Chip,” in Proceedings of the International Symposium on Networks-on-Chip, pp. 207-208, April 2008

    Google Scholar 

  25. L. Shang, L. S. Peh, and N. K. Jha, “Powerherd: a Distributed Scheme for Dynamically Satisfying Peak-Power Constraints in Interconnection Networks,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 1, pp. 92-110, January 2006

    Google Scholar 

  26. A. Banerjee, P. T. Wolkotte, R. D. Mullins, S. W. Moore, and G. J. M. Smit, “An Energy and Performance Exploration of Network-on-Chip Architectures,” IEEE Transactions on Very Large Scale Integration Systems, vol. 17, no. 3, pp. 319-329, March 2009

    Google Scholar 

  27. R. Ho, K. W. Mai, and M. A. Horowitz, “The Future of Wires,” Proceedings of the IEEE, vol. 89, no. 4, pp. 490-504, April 2001

    Google Scholar 

  28. International Technology Roadmap for Semiconductors: Executive Summary, Semiconductor Industry Association, 2007

    Google Scholar 

  29. F. Angiolini, P. Meloni, S. M. Carta, L. Raffo, and L. Benini, “A Layout-Aware Analysis of Networks-on-Chip and Traditional Interconnects for MPSoCs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 3, pp. 421-434, March 2007

    Google Scholar 

  30. I. Hatirnaz, S. Badel, N. Pazos, Y. Leblebici, S. Murali, D. Atienza, and G. DeMicheli, “Early Wire Characterization for Predictable Network-on-Chip Global Interconnects,” in Proceedings of the International Workshop on System Level Interconnect Prediction, pp. 57-64, March 2007

    Google Scholar 

  31. A. Pullini, F. Angiolini, S. Murali, D. Atienza, G. DeMicheli, and L. Benini, “Bringing NoCs to 65 nm,” IEEE Micro, vol. 27, no. 5, pp. 75-85, September 2007

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Sao-Jie Chen .

Rights and permissions

Reprints and permissions

Copyright information

© 2012 Springer Science+Business Media, LLC

About this chapter

Cite this chapter

Chen, SJ., Lan, YC., Tsai, WC., Hu, YH. (2012). Bidirectional Noc Architecture. In: Reconfigurable Networks-on-Chip. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-9341-0_6

Download citation

  • DOI: https://doi.org/10.1007/978-1-4419-9341-0_6

  • Published:

  • Publisher Name: Springer, New York, NY

  • Print ISBN: 978-1-4419-9340-3

  • Online ISBN: 978-1-4419-9341-0

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics