Communication Centric Design

  • Sao-Jie Chen
  • Ying-Cherng Lan
  • Wen-Chung Tsai
  • Yu-Hen Hu
Chapter

Abstract

As the density of VLSI design increases, the complexity of each component in a system raises rapidly. To accommodate the increasing transistor density, higher operating frequencies, and shorter time-to-market pressure, multi-processor System-on-Chip (MP-SoC) architectures, which use bus structures for on-chip communication and integrate complex heterogeneous functional elements on a single die, are more and more required in today’s semiconductor industry. However, today’s SoC designers face a new challenge in the design of the on-chip interconnects beyond the evolution of an increasing number of processing elements. Traditional bus-based communication schemes, which lack of scalability and predictability, are not capable to keep up with the increasing requirements of future SoCs in terms of performance, power, timing closure, scalability, and so on. To meet the design productivity and signal integrity challenges of next-generation system designs, a structured and scalable interconnection architecture, Network-on-Chip (NoC), has been proposed recently to mitigate the complex on-chip communication problem.

References

  1. 1.
    F. N. Najm, “A Survey of Power Estimation Techniques in VLSI Circuits,” IEEE Transactions on Very Large Scale Integrations Systems, vol. 2, no. 4, pp. 446–455, December 1994Google Scholar
  2. 2.
    R. Ho, K. W. Mai, and M. A. Horowitz, “The Future of Wires,” Proceedings of the IEEE, vol. 89, no. 4, pp. 490–504, April 2001Google Scholar
  3. 3.
    ARM, AMBA Specification Rev 2.0, ARM Limited, 1999Google Scholar
  4. 4.
    IBM, 32-bit Processor Local Bus Architecture Specification Version 2.9, IBM CorporationGoogle Scholar
  5. 5.
    L. Benini and G. DeMicheli, “Networks on Chips: a New SoC Paradigm,” IEEE Transactions on Computers, vol. 35, no. 4, pp. 70–78, January 2002Google Scholar
  6. 6.
    W. J. Dally and B. Towles, Principles and Practices of Interconnection Networks, Morgan Kaufmann, 2004Google Scholar
  7. 7.
    W. J. Dally and B. Towles, “Route Packets, Not Wires: On-Chip Interconnection Networks,” in Proceedings of the Design Automation Conference, pp. 684–689, June 2001Google Scholar
  8. 8.
    M. Kistler, M. Perrone, and F. Petrini, “Cell Multiprocessor Communication Network: Built for Speed,” IEEE Micro, vol. 26, no. 3, pp. 10–23, May 2006Google Scholar
  9. 9.
    L. Seiler, D. Carmean, E. Sprangle, T. Forsyth, P. Dubey, S. Junkins, A. Lake, R. Cavin, R. Espasa, E. Grochowski, T. Juan, M. Abrash, J. Sugerman, and P. Hanrahan, “Larrabee: A Many-Core x86 Architecture for Visual Computing,” IEEE Micro, vol. 29, no. 1, pp. 10–21, January 2009Google Scholar
  10. 10.
    D. Wentzlaff, P. Griffin, H. Hoffmann, L. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-Chip Interconnection Architecture of the Tile Processor,” IEEE Micro, vol. 27, no. 5, pp. 15–31, September 2007Google Scholar
  11. 11.
    J. Howard, S. Dighe, Y. Hoskote, S. Vangal, D. Finan, G. Ruhl, D. Jenkins, H. Wilson, N. Borkar, G. Schrom, F. Pailet, S. Jain, T. Jacob, S. Yada, S. Marella, P. Salihundam, V. Erraguntla, M. Konow, M. Riepen, G. Droege, J. Lindemann, M. Gries, T. Apel, K. Henriss, T. L. Larsen, S. Steibl, S. Borkar, V. De, R. Van Der Wijngaart, and T. Mattson, “A 48-Core IA-32 Message-Passing Processor with DVFS in 45nm CMOS,” in Proceedings of the IEEE International Solid-State Circuits Conference, pp. 108–109, February 2010Google Scholar
  12. 12.
    A. Hemani, A. Jantsch, S. Kumar, A. Postula, J. Oberg, M. Millberg, and D. Lindvist, “Network-on-Chip: an Architecture for Billion Transistor Era,” in Proceedings of the IEEE NorChip Conference, pp. 1–8, July 2000Google Scholar
  13. 13.
    S. Kumar, A. Jantsch, J. P. Soininen, M. Forsell, M. Millberg, J. Oberg, K. Tiensyrja, and A. Hemani, “A Network-on-Chip Architecture and Design Methodology,” in Proceedings of the International Symposium on Very Large Scale Integration, pp. 105–112, April 2000Google Scholar
  14. 14.
    R. Hegde and N. R. Shanbhag, “Toward Achieving Energy Efficiency in Presence of Deep Submicron Noise,” IEEE Transactions on Very Large Scale Integration Systems, vol. 8, no. 4, pp. 379–391, August 2000Google Scholar
  15. 15.
    C. Constantinescu, “Trends and Challenges in VLSI Circuit Reliability,” IEEE Micro, vol. 23, no. 4, pp. 14–19, July 2003Google Scholar
  16. 16.
    N. Cohen, T. S. Sriram, N. Leland, S. Butler, and R. Flatley, “Soft Error Considerations for Deep-Submicron CMOS Circuit Applications,” in Proceedings of the International Electron Devices Meeting Technical Digest, pp. 315–318, December 1999Google Scholar
  17. 17.
    P. Shivakumar, M. Kistler, S. Keckler, D. Burger, and L. Alvisi, “Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic,” in Proceeding of the Dependable Systems and Networks, pp. 389–398, June 2002Google Scholar
  18. 18.
    C. Grecu and M. Jones, “Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures,” IEEE Transactions on Computers, vol. 54, no. 8, August 2005Google Scholar
  19. 19.
    M. Rahmani, M. Daneshtalab, A. A. Kusha, S. Safari, and M. Pedram, “Forecasting-Based Dynamic Virtual-channels Allocation for Power Optimization of Network-on-Chips,” in Proceedings of the International Conference on VLSI Design, pp. 151–156, January 2009Google Scholar
  20. 20.
    N Kavaldjiev, G. Smit, and P. Jansen, “A Virtual-channel Router for on-Chip Networks,” in Proceedings of the System-on-Chip Conference, pp. 289–293, September 2004Google Scholar
  21. 21.
    W. J. Dally, “Virtual Channel Flow Control,” IEEE Transactions on Parallel and Distributed Systems, vol. 3, no. 2, pp. 194–205, March 1992Google Scholar
  22. 22.
    E. Rijpkema, K. G. W. Goossens, A. Radulescu, J. Dielissen, J. V. Meerbergen, P. Wielage, and E. Waterlander, “Trade-offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks-on-Chip,” in Proceedings of the Design Automation and Test in Europe Conference, pp. 350–355, March 2003Google Scholar
  23. 23.
    H. S. Wang, L. S. Peh, and S. Malik, “A Power Model for Routers: Modeling Alpha 21364 and InfiniBand Routers,” IEEE Micro, vol. 23, no. 1, 2003Google Scholar
  24. 24.
    R. Mullins, A. West, and S. Moore, “Low-Latency Virtual-Channel Routers for On-Chip Networks,” in Proceedings of the International Symposium on Computer Architecture, pp. 188–197, June 2004Google Scholar
  25. 25.
    K. Kim, S. J. Lee, K. Lee, and H. J. Yoo, “An Arbitration Look-ahead Scheme for Reducing End-to-End Latency in Networks-on-Chip.” in Proceedings of the International Symposium on Circuits and Systems, pp. 2357–2360, May 2005Google Scholar
  26. 26.
    P. Guerrier and A. Greiner, “A Generic Architecture for On-Chip Packet-Switched Interconnections,” in Proceedings of the Design Automation and Test in Europe Conference, pp. 250–256, Mar. 2000Google Scholar
  27. 27.
    M. R. Garey and D. S. Johnson, Computers and Intractability: a Guide to the Theory of NP-Completeness, Freeman and Company, 1979Google Scholar
  28. 28.
    R. Marculescu, U. Y. Ogras, L. S. Peh, N. E. Jerger, and Y. Hoskote, “Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 1, pp. 3–21, January 2009Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2012

Authors and Affiliations

  • Sao-Jie Chen
    • 1
  • Ying-Cherng Lan
    • 1
  • Wen-Chung Tsai
    • 1
  • Yu-Hen Hu
    • 2
  1. 1.National Taiwan UniversityTaipeiTaiwan R.O.C
  2. 2.University of Wisconsin-MadisonMadisonUSA

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