Communication Centric Design

  • Sao-Jie Chen
  • Ying-Cherng Lan
  • Wen-Chung Tsai
  • Yu-Hen Hu


As the density of VLSI design increases, the complexity of each component in a system raises rapidly. To accommodate the increasing transistor density, higher operating frequencies, and shorter time-to-market pressure, multi-processor System-on-Chip (MP-SoC) architectures, which use bus structures for on-chip communication and integrate complex heterogeneous functional elements on a single die, are more and more required in today’s semiconductor industry. However, today’s SoC designers face a new challenge in the design of the on-chip interconnects beyond the evolution of an increasing number of processing elements. Traditional bus-based communication schemes, which lack of scalability and predictability, are not capable to keep up with the increasing requirements of future SoCs in terms of performance, power, timing closure, scalability, and so on. To meet the design productivity and signal integrity challenges of next-generation system designs, a structured and scalable interconnection architecture, Network-on-Chip (NoC), has been proposed recently to mitigate the complex on-chip communication problem.


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Copyright information

© Springer Science+Business Media, LLC 2012

Authors and Affiliations

  • Sao-Jie Chen
    • 1
  • Ying-Cherng Lan
    • 1
  • Wen-Chung Tsai
    • 1
  • Yu-Hen Hu
    • 2
  1. 1.National Taiwan UniversityTaipeiTaiwan R.O.C
  2. 2.University of Wisconsin-MadisonMadisonUSA

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