Advertisement

Networks-on-Chip (NoC)

Chapter

Abstract

The move to many-core system is expected to become the dominant trend in the near future. With technology scaling into nanoscale regime, hundreds and even thousands of intellectual property (IP) cores can be integrated into a single chip. How to provide efficient and reliable communication between these IP cores becomes a bit problem. The conventional bus-based infrastructures are no longer sufficient to handle intensive on-chip communication. Network-on-chip (NoC) is emerging as an efficient solution to solve the aggravating scalability and bandwidth issues of on-chip communication by replacing traditional bus structures with a packet-switched network. This chapter is developed to introduce the common NoC architectures and the reliability issues facing in NoC design.

References

  1. 1.
    Gschwind M, Hofstee H, Flachs B et al (2006) Synergistic processing in Cell’s multicore architecture. IEEE Micro 26:10–24CrossRefGoogle Scholar
  2. 2.
    ARM AMBA specification and multilayer AHB specification (rev2.0). http://www.arm.com
  3. 3.
    ARM AMBA 3.0 AXI specification. http://www.arm.com/armtech/AXI
  4. 4.
    IBM CoreConnect specification. http://www.ibm.com/chips/techlib/techlib.nsf/product families/CoreConnect_Bus_Architecture
  5. 5.
    Wishbone specification. http://www.opencores.org/wishbone
  6. 6.
    Pasricha S, Dutt N, Ben-Romdhane M (2004) Fast exploration of bus-based on-chip communication architectures. In: International conference on hardware/software codesign and system synthesis (CODES_ISSS), pp 242–247Google Scholar
  7. 7.
    Mattson GT et al. (2010) The 48-core SCC processor: the programmer’s view. In: Proceedings of ACM/IEEE conference on supercomputing (SC), pp 1–11Google Scholar
  8. 8.
    Howard J et al (2011) A 48-core IA-32 processor in 45 nm CMOS using on-die message-passing and DVFS for performance and power scaling. IEEE J Solid-State Circuits 46:173–183CrossRefGoogle Scholar
  9. 9.
    Pande PP, Grecu C, Ivanov A, Saleh R (2005) Performance evaluation and design trade-offs for network-on-chip interconnect architectures. IEEE Trans Comput 54:1025–1040CrossRefGoogle Scholar
  10. 10.
    Millberg M, Nilsson E, Thid R, Jantsch A (2004) Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip. In: Proceedings of the design, automation and test in Europe conference and exhibition (DATE), pp 890–895Google Scholar
  11. 11.
    Wentzlaff D et al (2007) On-chip interconnection architecture of the tile processor. IEEE Micro 27:15–31CrossRefGoogle Scholar
  12. 12.
    Gratz P, Kim C, Sankaralingam K, Hanson H et al (2007) On-chip interconnection networks of the TRIPS chip. IEEE Micro 27:41–50CrossRefGoogle Scholar
  13. 13.
    Hoskote Y, Vangal S, Singh A, Borkar N, Borkar S (2007) A 5-GHz mesh interconnects for a teraflops processor. IEEE Micro 27:51–61CrossRefGoogle Scholar
  14. 14.
    Ilitzky AD, Hoffman DJ, Chun A, Esparza PB (2007) Architecture of the scalable communications core’s network on chip. IEEE Micro 27:62–74CrossRefGoogle Scholar
  15. 15.
    Sgroi M et al. (2001) Addressing the system-on-a-chip interconnect woes through communication-based design. In: Proceedings of 38th Design Automation Conference (DAC), pp 667–672Google Scholar
  16. 16.
    Bolotin E, Cidon I, Ginosar R, Kolodny A (2004) Cost considerations in network on chip. Integr VLSI J 38:19–42CrossRefGoogle Scholar
  17. 17.
    Dehyadgari M, Nickray M, Afzali-kusha A, Navabi Z (2005) Evaluation of pseudo adaptive XY routing using an object oriented model for NOC. In: The 17th international conference on microelectronicsGoogle Scholar
  18. 18.
    Bobda C, Ahmadinia A, Majer M et al (2005) DyNoC: a dynamic infrastructure for communication in dynamically reconfigurable devices. In: International conference on field programmable logic and applications, pp 153–158Google Scholar
  19. 19.
    Kariniemi H, Nurmi J (2004) Arbitration and routing schemes for on-chip packet networks. In: Interconnect-centric design for advanced SoC and NoC, pp 253–282Google Scholar
  20. 20.
    Dally JW, Towles B (2004) Principles and practices of interconnection networks. Morgan Kauffman, San FranciscoGoogle Scholar
  21. 21.
    Andriahantenaina A, Charlery H, Greiner A et al. (2003) SPIN: a scalable, packet switched, on-chip micro–network. In: Design automation and test in Europe conference and exhibition (DATE), pp 70–73Google Scholar
  22. 22.
    Kim J, Park D, Theocharides T et al. (2005) A low latency router supporting adaptivity for on-chip interconnects. In: Proceedings of 42nd design automation conference (DAC), pp 59–564.Google Scholar
  23. 23.
    Andreasson D, Kumar S (2005) Slack-time aware routing in NoC systems. In: IEEE international symposium on circuits and systems, pp 2353–2356Google Scholar
  24. 24.
    Wolkotte PT, Smit G, Rauwerda KG, Smit TL (2005) An energy-efficient reconfigurable circuit switched network-on-chip. In: Proceedings of the 19th IEEE international parallel and distributed processing symposium (IPDPS)Google Scholar
  25. 25.
    Kumar S, Jantsch A, Soininen PJ et al. (2002) A network on chip architecture and design methodology. In: Proceedings of IEEE computer society annual symposium on VLSI, pp 105–112Google Scholar
  26. 26.
    Wentzla D, Griffin P, Hoffmann H et al (2007) On-chip interconnection architecture of the tile processor. IEEE Micro 27:15–31CrossRefGoogle Scholar
  27. 27.
    Balfour J, Dally WJ (2006) Design tradeoffs for tiled CMP on-chip networks. In: 20th annual international conference on supercomputing, pp 187–198Google Scholar
  28. 28.
    Nicopoulos CA, Dongkook P, Jongman K et al (2006) ViChar: a dynamic virtual channel regulator for network-on-chip routers. In: 39th Annual IEEE/ACM international symposium on microarchitecture (MICRO), pp 333–346Google Scholar
  29. 29.
    Bjerregaard T, Mahadevan S (2006) A survey of research and practices of network-on-chip. Acm Comput Surv 38:1–51CrossRefGoogle Scholar
  30. 30.
    Lehtonen T, Wolpert D, Liljeberg P, Plosila J, Ampadu P (2010) Self-adaptive system for addressing permanent errors in on-chip interconnects. IEEE Trans Very Large Scale Integr (VLSI) Syst 18:527–540CrossRefGoogle Scholar
  31. 31.
    Bertozzi D, Benini L (2004) Xpipes: a network-on-chip architecture for gigascale systems-on-chip. IEEE Circuits Syst Mag 4:18–31CrossRefGoogle Scholar
  32. 32.
    Murali S, Theocharides T, Vijaykrishnan N, Irwin JM, Benini L, De Micheli G (2005) Analysis of error recovery schemes for networks-on-chips. IEEE Des Test Comput 22:434–442CrossRefGoogle Scholar
  33. 33.
    Pirretti M, Link MG, Brooks RR et al (2004) Fault tolerant algorithms for network-on-chip interconnect. In: IEEE computer society annual symposium on VLSI, pp 46–51Google Scholar
  34. 34.
    Dumitras T, Kerner S, Marculescu R (2003) Towards on-chip fault tolerant communication. In: Proceedings of ACM/IEEE design automation conference (DAC), pp 225–232Google Scholar
  35. 35.
    Sridhara S, Shanbhag RN (2005) Coding for system-on-chip networks: a unified framework. IEEE Trans Very Large Scale Integr (VLSI) Syst 13:655–667CrossRefGoogle Scholar
  36. 36.
    Bertozzi D, Benini L, De Micheli G (2005) Error control schemes for on-chip communication links: the energy-reliability tradeoff. IEEE Trans Computer-Aided Design Integr Circuits Syst 24:818–831CrossRefGoogle Scholar
  37. 37.
    Rossi D, Nieuwland KA, Katoch A, Metra C (2005) Exploiting ECC redundancy to minimize crosstalk impact. IEEE Des Test Comput 22:59–70CrossRefGoogle Scholar
  38. 38.
    Rossi D, Nieuwland KA, Dijk SVE, Kleihorst PR, Metra C (2008) Power consumption of fault tolerant busses. IEEE Trans Very Large Scale Integr (VLSI) Syst 16:542–553CrossRefGoogle Scholar
  39. 39.
    Worm F, Ienne P, Thiran P, Micheli DG (2005) A robust self-calibrating transmission scheme for on-chip networks. IEEE Trans Very Large Scale Integr (VLSI) Syst 13:126–139CrossRefGoogle Scholar
  40. 40.
    Ejlali A, Al-Hashimi MB, Rosinger P, Miremadi GS, Benini L (2010) Performability/energy tradeoff in error-control schemes for on-chip networks. IEEE Trans Very Large Scale Integr (VLSI) Syst 18:1–14CrossRefGoogle Scholar
  41. 41.
    Li L, Vijaykrishnan N, Kandemir M, Irwin JM (2003) Adaptive error protection for energy efficiency. In: Proceedings of IEEE/ACM international conference on computer-aided design (ICCAD), pp 2–7Google Scholar
  42. 42.
    Rossi D, Angelini P, Metra C (2007) Configurable error control scheme for NoC signal integrity. In: Proceedings of international on line testing symposium (IOLTS), pp 43–48Google Scholar
  43. 43.
    Fujiwara E (2006) Code design for dependable systems: theory and practical applications. Wiley, HobokenMATHCrossRefGoogle Scholar
  44. 44.
    Yu Q, Ampadu P (2008) Adaptive error control for NoC switch-to-switch links in a variable noise environment. In: Proceedings of IEEE international symposium on defect and fault tolerance in VLSI system (DFT), pp 352–360Google Scholar
  45. 45.
    Yu Q, Ampadu P (2009) Adaptive error control for nanometer scale NoC links. IET Comput Digit Tech 3:643–659 (Special issue on advances in nanoelectronics circuits and systems)CrossRefGoogle Scholar
  46. 46.
    Lehtonen T, Liljeberg P, Plosila J (2007) Online reconfigurable self-timed links for fault tolerant NoC, VLSI Design. Article ID 94676:13Google Scholar
  47. 47.
    Zimmer H, Jantsch A (2003) A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip. In: Proceedings of international conference hardware/software codesign and systems synthesis (CODES-ISSS), pp 188–193Google Scholar
  48. 48.
    Gangly A, Pande PP, Belter B, Grecu C (2008) Design of low power & reliable networks on chip through joint crosstalk avoidance and multiple error correction coding. J Electron Tes: Theory Apple (JETTA), 67–81 (Special issue on defect and fault tolerance)Google Scholar
  49. 49.
    Gangly A, Pande PP, Belter B (2009) Crosstalk-aware channel coding schemes for energy efficient and reliable NOC interconnects. IEEE Trans VLSI Syst 17:1626–1639CrossRefGoogle Scholar
  50. 50.
    Lehtonen T, Liljeberg P, Plosila J (2007) Analysis of forward error correction methods for nanoscale networks-on-chip. In: Proceedings of 2nd international conference on nano-networks (Nano-Net), pp 1–5Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2012

Authors and Affiliations

  1. 1.Marvell Semiconductor, Inc.Santa ClaraUSA
  2. 2.Department of Electrical and Computer EngineeringUniversity of RochesterRochesterUSA

Personalised recommendations