Low-Power Design of Turbo Decoder with Exploration of Energy-Throughput Trade-Off
Turbo coding has become an attractive scheme for design of current communication systems, providing near optimal bit error rates for data transmission at low signal to noise ratios. However, it is as yet unsuitable for use in high data rate mobile systems owing to the high energy consumption of the decoder scheme. Due to the data dominated nature of the decoder, a memory organization providing sufficient bandwidth is the main bottleneck for energy. We have systematically optimized the memory organization’s energy consumption using our Data Transfer and Storage Exploration methodology. This chapter discusses the exploration of the energy versus throughput trade-off for the turbo decoder module, which was obtained using our storage bandwidth optimization tool.
KeywordsTurbo Code State Metrics Memory Organization Memory Architecture Extrinsic Information
Unable to display preview. Download preview PDF.
- E. Brockmeyer, A. Vandecappelle, S. Wuytack, F. Catthoor. Low Power Storage Cycle Budget Distribution Tool Supportfor Hierarchical Graphs. 13th International Symposium on System Synthesis, pp. 20–22, Madrid, Spain. 2000.Google Scholar
- E. Brockmeyer, A. Vandecappelle, F. Catthoor. Systematic Cycle Budget versus System Power Trade-off: A New Perspective on System Exploration of Real-time Data-dominated Applications. International Symposium on Low Power Electronics and Design, pp. 137–142, Rapallo, Italy. 2000.Google Scholar
- F. Catthoor, S. Wuytack, E. de Greef, F. Balasa, L. Nachtergaele, A. Van decappelle. Custom Memory Management Methodology - Exploration of Memory Organisation for Embedded Multimedia System Design. ISBN 0-7923-8288-9, Kluwer Academic Publishers, Boston. 1998.Google Scholar
- F. Catthoor, K. Danckaert, C. Kulkarni, E. Brockmeyer, P-G. Kjeldsberg, T. van Achteren, T. Omnes. Data Access and Storage Management for Embedded Programmable Processors. Kluwer Academic Publishers, Boston. 2002.Google Scholar
- F. Gilbert, A. Worm, N. Wehn. Low Power Implementation of a Turbo Decoder on Programmable Architectures. Asia South Pacific Design Automation Conference (ASP-DAC), pp. 400–403, Yokohama, Japan. 2001.Google Scholar
- A. Giulietti, B. Bougard, V. Derudder, S. Dupont, J. W. Weijers, L. Van der Perre. A 80 Mb/s Low-power Scalable Turbo Codec Core. IEEE Custom Integrated Circuit Conference, pp. 389–392, Orlando, May 2002Google Scholar
- A. Giulietti, L. Van der Perre, M. Strum. Parallel turbo coding inter - leavers: avoiding collisions in accesses to storage elements lEE Electronics Letters, Vol. 38, No.5. February 2002.Google Scholar
- F. Maessen, A. Giuletti, B. Bougard, L. Van der Perre, F. Catthoor, M. Engels. Memory Power Reduction for the High-Speed Implementation of Turbo Codes. IEEE Workshop on Signal Processing Systems (SIPS) Design and Implementation, pp. 16–24, Antwerp, Belgium. September 2001.Google Scholar
- P. Robertson, P. Hoeher. Optimal and sub-optimal Maximum a Posteriori Algorithms Suitable for turbo decoding, IEEE International Conference on Communications, pp. 1009–1013, 1995Google Scholar
- C. E. Shannon. A Mathematical Theory of Communication. Bell System Technical Journal, Vol. 27, pp. 379–423, 623–656. 1948.Google Scholar
- Z. Wang, H. Suzuki, K. K. Parhi. VLSI Implementation Issues of Turbo Decoder Design for Wireless Applications. IEEE Workshop on Signal Processing Systems: Design and Implementation, Taipei. 1999.Google Scholar