Low-Power Design of Turbo Decoder with Exploration of Energy-Throughput Trade-Off

  • Arnout Vandecappelle
  • Bruno Bougard
  • K. C. Shashidhar
  • Francky Catthoor


Turbo coding has become an attractive scheme for design of current communication systems, providing near optimal bit error rates for data transmission at low signal to noise ratios. However, it is as yet unsuitable for use in high data rate mobile systems owing to the high energy consumption of the decoder scheme. Due to the data dominated nature of the decoder, a memory organization providing sufficient bandwidth is the main bottleneck for energy. We have systematically optimized the memory organization’s energy consumption using our Data Transfer and Storage Exploration methodology. This chapter discusses the exploration of the energy versus throughput trade-off for the turbo decoder module, which was obtained using our storage bandwidth optimization tool.


Turbo Code State Metrics Memory Organization Memory Architecture Extrinsic Information 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. [1]
    L. R. Bahl, J. Cocke, F. Jelinek, J. Raviv. Optimal Decoding of Linear Codes for Minimising Symbol Error Rate. IEEE Transactions on Information Theory, Vol. 20, pp. 284–287. 1974.MathSciNetMATHCrossRefGoogle Scholar
  2. [2]
    C. Berrou, A. Glavieux. Near Optimum Error Correcting, Coding and Decoding: Turbo Codes. IEEE Transactions on Communications, Vol. 44, No. 10, pp. 1261–1271. 1996.CrossRefGoogle Scholar
  3. [3]
    E. Brockmeyer, A. Vandecappelle, S. Wuytack, F. Catthoor. Low Power Storage Cycle Budget Distribution Tool Supportfor Hierarchical Graphs. 13th International Symposium on System Synthesis, pp. 20–22, Madrid, Spain. 2000.Google Scholar
  4. [4]
    E. Brockmeyer, A. Vandecappelle, F. Catthoor. Systematic Cycle Budget versus System Power Trade-off: A New Perspective on System Exploration of Real-time Data-dominated Applications. International Symposium on Low Power Electronics and Design, pp. 137–142, Rapallo, Italy. 2000.Google Scholar
  5. [5]
    F. Catthoor, S. Wuytack, E. de Greef, F. Balasa, L. Nachtergaele, A. Van decappelle. Custom Memory Management Methodology - Exploration of Memory Organisation for Embedded Multimedia System Design. ISBN 0-7923-8288-9, Kluwer Academic Publishers, Boston. 1998.Google Scholar
  6. [6]
    F. Catthoor, K. Danckaert, C. Kulkarni, E. Brockmeyer, P-G. Kjeldsberg, T. van Achteren, T. Omnes. Data Access and Storage Management for Embedded Programmable Processors. Kluwer Academic Publishers, Boston. 2002.Google Scholar
  7. [7]
    H. Dawid, H. Meyr. Real-time Algorithms and VLSI Architectures for Soft Output MAP Convolutional Decoding. 6th IEEE International Symposium on Personal, Indoor and Mobile Radio Communications, Vol. 1, pp. 193–197. 1995.CrossRefGoogle Scholar
  8. [8]
    F. Gilbert, A. Worm, N. Wehn. Low Power Implementation of a Turbo Decoder on Programmable Architectures. Asia South Pacific Design Automation Conference (ASP-DAC), pp. 400–403, Yokohama, Japan. 2001.Google Scholar
  9. [9]
    A. Giulietti, B. Bougard, V. Derudder, S. Dupont, J. W. Weijers, L. Van der Perre. A 80 Mb/s Low-power Scalable Turbo Codec Core. IEEE Custom Integrated Circuit Conference, pp. 389–392, Orlando, May 2002Google Scholar
  10. [10]
    A. Giulietti, L. Van der Perre, M. Strum. Parallel turbo coding inter - leavers: avoiding collisions in accesses to storage elements lEE Electronics Letters, Vol. 38, No.5. February 2002.Google Scholar
  11. [11]
    S. Hong, W. E. Stark et al. Design and Implementation of a Low Complexity VLSI Turbo-Code Decoder Architecture for Low Energy Mobile Wireless Communications. Journal of VLSI Signal Processing, Vol. 24, No.1, pp. 43–57. 2000.MATHCrossRefGoogle Scholar
  12. [12]
    F. Maessen, A. Giuletti, B. Bougard, L. Van der Perre, F. Catthoor, M. Engels. Memory Power Reduction for the High-Speed Implementation of Turbo Codes. IEEE Workshop on Signal Processing Systems (SIPS) Design and Implementation, pp. 16–24, Antwerp, Belgium. September 2001.Google Scholar
  13. [13]
    G. Masera, G. Piccinini, M. R. Roch, M. Zamboni. VLSI Architectures for Turbo Codes. IEEE Transactions on VLSI Systems, Vol. 7. No.3, pp. 369–379. 1999.CrossRefGoogle Scholar
  14. [14]
    P. Robertson, P. Hoeher. Optimal and sub-optimal Maximum a Posteriori Algorithms Suitable for turbo decoding, IEEE International Conference on Communications, pp. 1009–1013, 1995Google Scholar
  15. [15]
    C. Schurgers, F. Catthoor, M. Engels. Memory Optimization of MAP Turbo Decoder Algorithms. IEEE Transactions on VLSI Systems, Vol. 9, No.2, pp. 305–312. 2001.CrossRefGoogle Scholar
  16. [16]
    C. E. Shannon. A Mathematical Theory of Communication. Bell System Technical Journal, Vol. 27, pp. 379–423, 623–656. 1948.Google Scholar
  17. [17]
    Z. Wang, H. Suzuki, K. K. Parhi. VLSI Implementation Issues of Turbo Decoder Design for Wireless Applications. IEEE Workshop on Signal Processing Systems: Design and Implementation, Taipei. 1999.Google Scholar

Copyright information

© Springer Science+Business Media New York 2003

Authors and Affiliations

  • Arnout Vandecappelle
    • 1
  • Bruno Bougard
    • 1
  • K. C. Shashidhar
    • 1
  • Francky Catthoor
    • 1
  1. 1.IME CvzwLeuvenBelgium

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