Wafer Scale Nanoimprint Lithography

  • Lars Montelius
  • Babak Heidari
Part of the Nanostructure Science and Technology book series (NST)


Nanoimprint lithography (NIL) got large attention when it was introduced 1, 2 since it de-scribed the possibility for a low cost parallel nanotechnology. It got even larger attention when it was reported that sub 10 nm features on a Si stamp could be replicated into a resist layer, which in turn had a profile allowing a lift-off process to be possible.3,4 More reports about NIL technology followed and soon also devices were reported made with NIL. 5, 6, 7 This development inspired a few research groups to initiate projects around NIL technology. Also related techniques such as micro contact printing and its relatives were further developed at this time. 8, 9 Several different nanoimprint machines, set-ups and processes were reported. Examples of this rich development are for instance the roller imprint, 10 Step and flash imprint lithography, 11 described multi-layer resist methods. 12 An interesting observation is that in most of the works reported so far (except the early works in ref. 2,3 above) the feature sizes have rather been closer to the 100 nm domain than to the 10 nm domain. Furthermore in most of the NIL experiments reported the de-scribed were made with stamps having areas of only one or a few square centimetre(s).1, 2, 3, 4, 5, 6, 7 In order to meet the demand from industries, there was thus a need to develop a large area NIL process.13 Here two alternatives exists, either use a full wafer single printing step procedure 14, 15, 16 or to utilize a step & repeat procedure.17 Still up to now, more than seven years ago after its introduction, very few reports of real large wafer scale NIL exists. The largest size of the wafers successfully printed is 6 inch 14, 15 and for these experiments two kinds of stamps has been used. The stamp was either a metal CD-master stamp or an de-scribed defined electroplated metal stamp having regions with lines at the nanometer scale distributed at few locations over the wafer. The printed pattern definition in the resist to be accurate.


Scanning Electron Micro Junction Temperature NANOIMPRINT Lithography Thermal Nonequilibrium Wafer Scale 
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Copyright information

© Springer Science+Business Media New York 2003

Authors and Affiliations

  • Lars Montelius
    • 1
  • Babak Heidari
    • 1
  1. 1.Div. of Solid State Physics & The Nanometer ConsortiumLund UniversityLundSweden

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