Performance of Memory Expansion Technology (MXT)
A novel memory subsystem called Memory Expansion Technology (MXT) has been built for fast hardware compression of main memory contents. This allows a system with memory expansion to present a real memory larger than the physically available memory. This chapter provides an overview of the memory compression architecture, the OS support, and an analysis of the performance impact of memory compression while running multiple benchmarks. Results show that the hardware compression of main memory has a negligible penalty compared to an uncompressed memory, and for memory starved applications it increases performance significantly. We also show that an applications’ memory contents can be compressed usually by a factor of 2.
KeywordsCompression Ratio Main Memory Memory Size Standard System Cache Line
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- 1.B. Abali and H. Franke. Operating System Support for Fast Hardware Compression of Main Memory. In Memory Wall Workshop, June 2000, also published as IBM Research Report No. RC21964, IBM, Yorktown Heights, NY.Google Scholar
- 3.B. Abali, H. Franke, D.E. Poff, X. Shen, and T.B. Smith. Performance of Hardware Compressed Main Memory. In Proceedings of The Seventh International Symposium on High Performance Computer Architecture (HPCA-7), pages 73–81, January 2001.Google Scholar
- 4.I.-C.K. Chen, J.T. Coffey, and T.N. Mudge. Analysis of Branch Prediction via Data Compression. Computer Architecture News, 24:128–137, October 1996.Google Scholar
- 6.P. Franaszek, P. Heidelberger, and M. Wazlowski. On Management of Free Space in Compressed Memory Systems. In Proceedings of the ACM Sigmetrics Conference, pages 113–121, June 1999.Google Scholar
- 8.P. Franaszek, J. Robinson, and J. Thomas. Compression architecture for system memory application. In Proceedings of the Data Compression Conference (DCC), pages 200–209, 1996.Google Scholar
- 9.J. Kalamatianos and D.R. Kaeli. Predicting Indirect Branches via Data Compression. In Proceedings of the Annual International Symposium on Microarchitecture, pages 272–281, 1998.Google Scholar
- 11.S.Y. Larin and T.M. Conte. Compiler-Driven Cached Code Compression Schemes for Embedded ILP Processors. In Proceedings of the Annual International Symposium on Microarchitecture, pages 82–92, 1999.Google Scholar
- 12.D. A. Luick, J.D. Brown, K.H. Haselhorst, S.W. Kerchberger, and W.P. Hovis. Compression Architecture for System Memory Application. US Patent 5,812,817, 1998.Google Scholar
- 14.P. Wilson, S. Kaplan, and Y. Smaragdakis. The Case for Compressed Caching in Virtual Memory Systems. In Proceedings of the USENIX Annual Technical Conference, 1999.Google Scholar