Evaluation of Large L3 Caches Using TPC-H Trace Samples
In this chapter we evaluate the miss rates of four L3 cache architectures for small-scale multiprocessors. Eight processors are partitioned into 1, 2, 4, or 8 clusters with 8, 4, 2, or 1 processors, respectively. Each cluster has a large L3 cache, and the aggregate amount of L3 cache in each of the four architectures varies between 64 MB and 1 GB. The target of our evaluations is decision support systems. We use bus trace samples obtained during the execution of a 100 GB TPC-H on an 8-way multiprocessor. These 12 time samples were taken at one hour intervals during the first day of execution of TPC-H. Each sample contains 64 M bus references.
We first show the distribution of bus references across samples and across processors in the same sample. The major problem with time samples is the cold start misses at the beginning of each sample. We show the cache warm-up rate for all cluster architectures and cache sizes. Unfortunately, systems with aggregate L3 cache sizes above 128 MB are never completely warm with our samples of size 64 million. Thus we evaluate cache architectures under three conditions: cold cache at the beginning of each sample, warm sets only, and stitched trace. We classify misses to understand their cause. Observations are similar across all three simulation types. We also show that the 12 time samples exhibit similar behavior.
One of the major observations using the twelve 64 M reference trace samples is the large number of interprocessor and IO coherence misses.
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