3-Level Buck Converter Microelectronic Implementation
This chapter covers the microelectronic design and implementation of the 3-level converter design obtained in Chap. 6. The implementation of such design not only requires the integration of the reactive components and the power switches and drivers, but also includes the additional circuitry required to obtain the appropriate DCM operation.Therefore, the first section covers the design of all the required control circuits (which in this work are called as the secondary control loop). These include the implementation of two different control loops to assure near ideal dead-time switching, as well as the turn-off of the NMOS switches at zero inductor current. Additionally, the building blocks to generate all the required switching signals are also exposed. For all the presented circuits, the corresponding layout design is provided. In the second section, details about the power components layout are explained. Finally, the third section presents transistor-level simulation results from the complete developed system (including the power converter itself and the required control circuits), as well as the general layout distribution.
KeywordsSwitching Frequency Layout Design Inductor Current Power Switch NMOS Transistor
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- 25.B. Arbetter and D. Maksimovic. DC-DC converter with fast transient response and high efficiency for low-voltage microprocessor loads. In Applied Power Electronics Conference and Exposition, 1998. APEC ’98. Conference Proceedings 1998., 13th Annual, volume 1, pages 156–162, Anaheim, CA, February 1998.Google Scholar
- 94.A. J. Stratakos, S. R. Sanders, and R. W. Brodersen. A low-voltage CMOS DC-DC converter for a portable battery-operated system. In Power Electronics Specialists Conference, PESC ’94 Record., 25th Annual IEEE, pages 619–626, Taipei, June 1994.Google Scholar
- 105.Sang-Hwa Jung, Nam-Sung Jung, Jong-Tae Hwang, and Gyu-Hyeong Cho. An integrated CMOS DC-DC converter for battery-operated systems. In Power Electronics Specialists Conference, 1999. PESC 99. 30th Annual IEEE, volume 1, pages 43–47, Charleston, SC, June/July 1999.Google Scholar
- 113.Wai Lau and S. R. Sanders. An integrated controller for a high frequency buck converter. In Power Electronics Specialists Conference, 1997. PESC ’97 Record., 28th Annual IEEE, volume 1, pages 246–254, St. Louis, MO, June 1997.Google Scholar
- 114.B. Acker, C. R. Sullivan, and S. R. Sanders. Synchronous rectification with adaptive timing control. In Power Electronics Specialists Conference, 1995. PESC ’95 Record., 26th Annual IEEE, volume 1, pages 88–95, Atlanta, GA, June 1995.Google Scholar
- 115.O. Trescases, Wai Tung Ng, and Shuo Chen. Precision gate drive timing in a zero-voltage-switching DC-DC converter. In Power Semiconductor Devices and ICs, 2004. Proceedings. ISPSD ’04. The 16th International Symposium on, pages 55–58, May 2004.Google Scholar
- 116.S. Mapus. Predictive gate drive boosts synchronous DC/DC power converter efficiency. Technical Report, Appl. Rep. SLUA281, Texas Instruments, 2003.Google Scholar
- 117.J. Kimball and P. T. Krein. Continuous-time optimization of gate timing for synchronous rectification. In Circuits and Systems, 1996., IEEE 39th Midwest symposium on, volume 3, pages 1015–1018, Ames, IA, August 1996.Google Scholar
- 118.A. V. Peterchev and S. R. Sanders. Digital loss-minimizing multimode synchronous buck converter control. In Power Electronics Specialists Conference, 2004. PESC 04. 2004 IEEE 35th Annual, volume 5, pages 3694–3699, June 2004.Google Scholar
- 119.V. Yousefzadeh and D. Maksimovic. Sensorless optimization of dead times in DC-DC converters with synchronous rectifiers. In Applied Power Electronics Conference and Exposition, 2005. APEC 2005. 20th Annual IEEE, volume 2, pages 911–917, March 2005.Google Scholar