The problem of synthesising accelerator data paths is an important one in the context of mapping high-throughput real-time signal processing applications onto ASIC architectures. It will become even more important now that a diverse range of advanced multimedia applications (including video and image processing) is gradually appearing on the consumer electronics market. In this book, a methodology that is supported by optimising CAD techniques has been proposed to solve this growing design problem.
KeywordsFlow Graph Operation Cluster Redundancy Removal Quadratic Binary Programme Address Generation Unit
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