An ART1/ARTMAP/Fuzzy-ART/Fuzzy-ARTMAP Chip
In this Chapter we present a new design approach for a Second Generation ART chip. This chip would be able to emulate the ART1, Fuzzy-ART, ARTMAP, and Fuzzy-ARTMAP architectures, and using both choice functions possibilities: subtraction and division for computing the Tj terms. The synaptic cells for this chip operate in weak inversion, so that chip size can be scaled up easily without worrying too much about power dissipation limitations. Also, the synaptic cells present a very high area density: we estimate that for a 1cm2 chip in a 0.5μm CMOS process with 3 metal layers, an ART1 (or simplified ARTMAP) system with N = 385 input nodes and M = 430 category nodes can be implemented; or if used as Fuzzy-ART (or simplified Fuzzy-ARTMAP) it could be of N = 77 input nodes and M = 430 category nodes.
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