Abstract
The key to working silicon usually lies in successful completion of static timing analysis performed on a particular design. PT is a stand-alone tool by Synopsys that is used to perform static timing analysis. It not only checks the design for required constraints that are governed by the design specifications, but also performs comprehensive analysis of the design. This capability makes STA one of the most important steps in the entire design flow and is used by many designers as a sign-off criterion to the ASIC vendor.
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© 1999 Springer Science+Business Media New York
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Bhathagar, H. (1999). Static Timing Analysis. In: Advanced ASIC Chip Synthesis. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-8668-9_12
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DOI: https://doi.org/10.1007/978-1-4419-8668-9_12
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-4662-3
Online ISBN: 978-1-4419-8668-9
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