Parallel Algorithm Synthesis Procedure
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The Parallel Algorithm Synthesis Procedure introduces parameters to control the partitioning and scheduling of computation and communication. The goal is to design and implement parameterized software components that can be tailored to exploit multiple scalar units within a single processor, hierarchical memories, and different configurations of multiple processors. At the heart of the synthesis procedure is a computational model that provides a qualitative framework for introducing parameters to improve reuse in the register file and memory hierarchy, balancing the load among P processors, and reducing data traffic over the processor interconnection network.
KeywordsShared Memory Algorithm Designer Register File Memory Hierarchy Scalar Unit
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