Parallel Algorithm Synthesis Procedure

Part of the Series in Computer Science book series (SCS)


The Parallel Algorithm Synthesis Procedure introduces parameters to control the partitioning and scheduling of computation and communication. The goal is to design and implement parameterized software components that can be tailored to exploit multiple scalar units within a single processor, hierarchical memories, and different configurations of multiple processors. At the heart of the synthesis procedure is a computational model that provides a qualitative framework for introducing parameters to improve reuse in the register file and memory hierarchy, balancing the load among P processors, and reducing data traffic over the processor interconnection network.


Shared Memory Algorithm Designer Register File Memory Hierarchy Scalar Unit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Copyright information

© Springer Science+Business Media New York 2003

Authors and Affiliations

  1. 1.Mercury Computer System, Inc.ChelmsfordUSA
  2. 2.John Hopkins UniversityBaltimoreUSA

Personalised recommendations