Abstract
This chapter extends some of the concepts introduced in earlier chapters, and applies them to the IP, subsystem, and chip level.
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© 2011 Synopsys, Inc.
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Keating, M. (2011). Complexity at the Chip Level. In: The Simple Art of SoC Design. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-8586-6_9
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DOI: https://doi.org/10.1007/978-1-4419-8586-6_9
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Publisher Name: Springer, New York, NY
Print ISBN: 978-1-4419-8585-9
Online ISBN: 978-1-4419-8586-6
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