Simplifying RTL Design



The basic challenge in RTL design is that there are a lot of things going on at the same time. The design of hardware involves dealing with concurrency. And ­currency is inherently a difficult problem.


Sequential Code State Machine Start Signal Hardware Description Language Synthesis Tool 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Copyright information

© Synopsys, Inc. 2011

Authors and Affiliations

  1. 1.SynopsysPalo AltoUSA

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