Abstract
The extensions described in this chapter focus on providing an efficient finite state machine primitive for SystemVerilog. In earlier chapters, we described the challenges of state machine design and the value of reducing state space to a minimum. Using a hierarchical finite state machine can significantly reduce the complexity of a design, often by several orders of magnitude. But there is no explicit support in SystemVerilog for FSMs in general or for hierarchical FSM specifically. Thus, there is no uniform way of coding them.
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© 2011 Synopsys, Inc.
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Keating, M. (2011). SystemVerilog Extensions. In: The Simple Art of SoC Design. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-8586-6_11
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DOI: https://doi.org/10.1007/978-1-4419-8586-6_11
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