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Delay Fault Diagnosis

  • Mukund Sivaraman
  • Andrzej J. Strojwas

Abstract

Testing fabricated chips for correct temporal behavior is typically done by applying a set of input vector pairs at-speed to the chip under test, and comparing the sampled circuit outputs with their expected logic values. Assuming that the chip is functionally correct, i.e., it produces the correct output values given sufficient time, any discrepancy is the result of one or more delay faults in the fabricated chip. Literature in this context has primarily focused on finding minimal delay test sets with maximal coverage [67][68][69][70][71], i.e., finding a small number of tests which will detect as many delay faults in the circuit as possible. By generating tests which can detect many delay faults in a circuit, the ability to determine which delay fault caused the chip failure gets diminished. Diagnostic testing [87] [88] deals with enhancing the diagnostic ability of tests, i.e., finding test sets which can not only detect delay faults but also distinguish between them.

Keywords

Path Delay Robust Test Circuit Output Benchmark Circuit Delay Fault 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 1998

Authors and Affiliations

  • Mukund Sivaraman
    • 1
  • Andrzej J. Strojwas
    • 1
  1. 1.Carnegie Mellon UniversityPittsburghUSA

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