Low-Power High-Performance Adders

  • Muhammad S. Elrabaa
  • Issam S. Abu-Khater
  • Mohamed I. Elmasry
Part of the The Springer International Series in Engineering and Computer Science book series (SECS, volume 405)


The scaling of the CMOS channel length to below 0.5 um and increasing of the chip density to the ULSI range have placed power dissipation on an equal footing with the performance as a figure of merit in digital circuit design. Portability and reliability [1] have also played a major role in the emergence of low-power, low-voltage, digital circuit designs. The need to extend the battery life, to have inexpensive packaging and cooling systems, and to reduce the weight and size of the equipment were the driving forces in this regard.


Supply Voltage Power Dissipation Critical Path PMOS Transistor Critical Delay Path 
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Copyright information

© Springer Science+Business Media New York 1997

Authors and Affiliations

  • Muhammad S. Elrabaa
    • 1
  • Issam S. Abu-Khater
    • 1
  • Mohamed I. Elmasry
    • 2
  1. 1.Intel CorporationUSA
  2. 2.University of WaterlooUSA

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