Algorithms of Generation Boolean Equations for a Multiplication Operation

Abstract

The article presents a critical analysis of existing methods for multiplication operations. It shows a development necessary for them to be used in a programmable integrated circuit. This extension mainly ranges a method for the generation of a result in an easy way to optimize set of Boolean equations. Finally there are two methods described of generation of logical equations for the multiplication instruction destined for integrated circuits synthesis. Both of them deal with integer type arguments, but there are two variables in the case of the first algorithm and a variable with a constant value in the case of the second one. The result of those processes is a product represented by a set of Boolean equations that describes a designed logical unit. Every bit of the result is represented by a logical equation. There are also temporary variables created during compilation to store partial equations. The paper also describes problems that appear during the optimization the algorithms presented. It estimates the number of generated equations and compilation time.