Abstract
One of the most important developments in the wireless industry within the last decade was the digitization of RF circuitry. This was in response to the incredible advancements of the mainstream CMOS technology in both processing speed and circuit density, as well as the relentless push to reduce total solution costs through integration of RF, analog and digital circuitry. Since the digital baseband part of a wireless communication channel has been traditionally implemented in the most advanced CMOS technology available at a given time for mass production, the need for single-chip CMOS integration has forced permanent changes to the way RF circuits are fundamentally designed. In this low-voltage nanometer-scale CMOS environment, the high-performance RF circuits must exploit the time-domain design paradigm and heavily rely on digital assistance. This chapter revisits the digitization journey of RF circuits and offers a glimpse into the future of digital RF technology.
Keywords
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsReferences
R. B. Staszewski, “Digital RF technology for expanding programmability of RF transceivers,” SK Telecom Journal - Reconfigurable RF Systems, vol. 20, no. 5, pp. 721–738, Oct. 2010.
F. M. Gardner, “Charge-pump phase-locked loops,” IEEE Trans. on Communications, vol. COMM-28, pp. 1849–1858, Nov. 1980.
B. Razavi, RF Microelectronics, Upper Saddle River, NJ: Prentice Hall, 1998.
T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge, UK: Cambridge University Press, 1998.
A. A. Abidi, “RF CMOS comes of age,” IEEE Journal of Solid-State Circuits, vol. 39, iss. 4, pp. 549–561, April 2004.
A. Matsuzawa, “Digital-centric RF CMOS technology,” IEEE Radio-Frequency Integration Technology (RFIT) Conf., pp. 122–126, Dec. 2007.
R. B. Staszewski, K. Muhammad, D. Leipold, C.-M. Hung, Y.-C. Ho, J. L. Wallberg, C. Fernando, K. Maggio, R. Staszewski, T. Jung, J. Koh, S. John, I. Y. Deng, V. Sarda, O. Moreira-Tamayo, V. Mayega, R. Katz, O. Friedman, O. E. Eliezer, E. de-Obaldia, and P. T. Balsara, “All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 39, iss. 12, pp. 2278–2291, Dec. 2004.
R. B. Staszewski, J. Wallberg, S. Rezeq, C.-M. Hung, O. Eliezer, S. Vemulapalli, C. Fernando, K. Maggio, R. Staszewski, N. Barton, M.-C. Lee, P. Cruise, M. Entezari, K. Muhammad, and D. Leipold, “All-digital PLL and transmitter for mobile phones,” IEEE Journal of Solid-State Circuits, vol. 40, iss. 12, pp. 2469–2482, Dec. 2005.
T. H. Lee, “CMOS RF: (Still) no longer an oxymoron,” Proc. of Symposium on Radio Frequency Integrated Circuits, pp. 3–6, 1999.
R. B. Staszewski, “Digital deep-submicron CMOS frequency synthesis for RF wireless applications,” Ph. D. thesis, Univ. of Texas at Dallas, Aug. 2002.
R. B. Staszewski and P. T. Balsara, All-Digital Frequency Synthesizer in Deep-Submicron CMOS, New Jersey: John Wiley & Sons, Inc., Sept. 2006.
R. B. Staszewski, D. Leipold, O. Eliezer, M. Entezari, K. Muhammad, I. Bashir, C.-M. Hung, J. Wallberg, R. Staszewski, P. Cruise, S. Rezeq, S. Vemulapalli, K. Waheed, N. Barton, M.-C. Lee, C. Fernando, K. Maggio, T. Jung, I. Elahi, S. Larson, T. Murphy, G. Feygin, I. Deng, T. Mayhugh, Y.-C. Ho, K.-M. Low, C. Lin, J. Jaehnig, J. Kerr, J. Mehta, S. Glock, T. Almholt, S. Bhatara, “A 24mm2 quad-band single-chip GSM radio with transmitter calibration in 90nm digital CMOS,” Proc. of IEEE Solid-State Circuits Conf., sec. 10.5, pp. 208–209, 607, Feb. 2008.
J. Mehta, R. B. Staszewski, O. Eliezer, S. Rezeq, K. Waheed, M. Entezari, G. Feygin, S. Vemulapalli, V. Zoicas, C.-M. Hung, N. Barton, I. Bashir, K. Maggio, M. Frechette, M.-C. Lee, J. Walberg, P. Cruise, N. Yanduru, “A 0.8 mm2 all-digital SAW-less polar transmitter in 65nm EDGE SoC,” Proc. of IEEE Solid-State Circuits Conf., sec. 3.2, pp. 58–59, Feb. 2010, San Francisco, CA, USA.
F. O. Eynde, J.-J. Schmit, V. Charlier, R. Alexandre, C. Sturman, K. Coffin, B. Moliekens, J. Craninckx, S. Terrijn, A. Monterastelli, S. Beerens, P. Goetschalckx, M. Ingels, D. Joos, S. Guncer, and A. Pontioglu, “A fully-integrated single-chip SOC for Bluetooth,” Proc. of IEEE Solid-State Circuits Conf., sec. 13.1, pp. 196–197, 446, Feb. 2001.
P. H. Bonnaud, M. Hammes, A. Hanke, J. Kissing, R. Koch, E. Labarre, and C. Schwoerer, “A fully integrated SoC for GSM/GPRS in 0.13μm CMOS,” Proc. of IEEE Solid-State Circuits Conf., pp. 482–483, 667, Feb. 2006.
S. Mehta, W. W. Si, H. Samavati, M. Terrovitis, M. Mack, K. Onodera, S. Jen, S. Luschas, J. Hwang, S. Mendis, D. Su, and B. Wooley, “A 1.9GHz single-chip CMOS PHS cellphone,” Proc. of IEEE Solid-State Circuits Conf., pp. 484–485, 668, Feb. 2006.
D. Weber, W. Si, S. Abdollahi-Alibeik, M.-L. Lee, R. Chang, H. Dogan, S. Luschas, and P. Husted, “A single-chip CMOS radio SoC for v2.1 Bluetooth applications,” Proc. of IEEE Solid-State Circuits Conf., sec. 20.5, pp. 364–365, 620, Feb. 2008.
L. Nathawad, M. Zargari, H. Samovati, S. Mehta, A. Kheirkhahi, P. Chen, K. Gong, B. Vakili-Amini, J. Hwang, M. Chen, M. Terrovitis, B. Kaczynski, S. Limotyrakis, M. Mack, H. Gan, M. Lee, S. Abdollahi-Alibeik, B. Baytekin, K. Onodera, S. Mendis, A. Chang, S. Jen, D. Su, and B. Wooley, “A dual-band CMOS MIMO radio SoC for IEEE 802.11n wireless LAN,” Proc. of IEEE Solid-State Circuits Conf., sec. 20.2, pp. 358–359, 619, Feb. 2008.
R. B. Staszewski, I. Bashir, and O. Eliezer, “RF built-in self test of a wireless transmitter,” IEEE Trans. on Circuits and Systems II, vol. 54, no. 2, pp. 186–190, Feb. 2007.
K. Muhammad, Y.-C. Ho, T. Mayhugh, C.-M. Hung, T. Jung, I. Elahi, C. Lin, I. Deng, C. Fernando, J. Wallberg, S. Vemulapalli, S. Larson, T. Murphy, D. Leipold, P. Cruise, J. Jaehnig, M.-C. Lee, R. B. Staszewski, R. Staszewski, and K. Maggio, “The first fully integrated quad-band GSM/GPRS receiver in a 90nm digital CMOS process,” IEEE Journal of Solid-State Circuits, vol. 41, iss. 8, pp. 1772–1783, Aug. 2006.
R. B. Staszewski, J. Wallberg, C.-M. Hung, G. Feygin, M. Entezari, and D. Leipold, “LMS-based calibration of an RF digitally-controlled oscillator for mobile phones,” IEEE Trans. on Circuits and Systems II, vol. 53, no. 3, pp. 225–229, Mar. 2006.
“GSM Specification: Radio Transmission and Reception, GSM 05.05 version 8.5.1,” ETSI EN 300 910, http://www.etsi.org, Nov. 2000.
R. Staszewski, R. B. Staszewski, T. Jung, T. Murphy, I. Bashir, O. Eliezer, K. Muhammad, and M. Entezari, “Software assisted Digital RF Processor (DRPTM) for single-chip GSM radio in 90 nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 45, iss. 2, pp. 276–288, Feb. 2010.
M. H. Perrott, R. T. Rex, and Y. Huang, “Digitally-synthesized loop filter circuit particularly useful for a phase locked loop,” US patent 6,630,868, issued Oct. 7, 2003.
A. Kajiwara, M. Nakagawa, “A new PLL frequency synthesizer with high switching speed,” IEEE Trans. on Vehicular Technology, vol. 41, no. 4, pp. 407–413, Nov 1992.
S.-Y. Yang, W.-Z. Chen, and T.-Y. Lu, “A 7.1 mW, 10 GHz all digital frequency synthesizer with dynamically reconfigured digital loop filter in 90 nm CMOS technology,” IEEE J. Solid-State Circuits, vol. 45, no. 3, pp. 578–586, Mar. 2010.
W.-H. Wu, J. R. Long, and R. B. Staszewski, “A digital ultra-fast acquisition linear frequency modulated PLL for mm-wave FMCW radars,” Proc. of IEEE Symp. on Radio-Frequency Integration Technology (RFIT) Conf., pp. 32–35, Dec. 2009.
R. B. Staszewski, C.-M. Hung, D. Leipold, and P. T. Balsara, “A first multigigahertz digitally controlled oscillator for wireless applications,” IEEE Trans. on Microwave Theory and Techniques, vol. 51, no. 11, pp. 2154–2164, Nov. 2003.
R. B. Staszewski, D. Leipold, K Muhammad and P. T. Balsara, “Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS process,” IEEE Trans. on Circuits and Systems II, vol. 50, no. 11, pp. 815–828, Nov. 2003.
R. B. Staszewski, S. Vemulapalli, P. Vallur, J. Wallberg, and P. T. Balsara “1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS,” IEEE Trans. on Circuits and Systems II, vol. 53, no. 3, pp. 220–224, Mar. 2006.
R. B. Staszewski, G. Shriki, and P. T. Balsara, “All-digital PLL with ultra fast acquisition,” Proc. of IEEE Asian Solid-State Circuits Conf., sec. 11-7, pp. 289–292, Nov. 2005, Taipei, Taiwan.
R. B. Staszewski, C. Fernando, and P. T. Balsara, “Event-driven simulation and modeling of phase noise of an RF oscillator,” IEEE Trans. on Circuits and Systems I, vol. 52, no. 4, pp. 723–733, Apr. 2005.
J.-C. Zhuang, K. Waheed, and R. B. Staszewski, “A technique to reduce phase/frequency modulation bandwidth in a polar RF transmitter,” IEEE Trans. on Circuits and Systems I, vol. 57, iss. 8, pp. 2196–2207, Aug. 2010.
I. L. Syllaios, P. T. Balsara, and R. B. Staszewski, “Recombination of envelope and phase paths in wideband polar transmitters,” IEEE Trans. on Circuits and Systems I, vol. 57, iss. 8, pp. 1891–1904, Aug. 2010.
R. B. Staszewski, D. Leipold, and P. T. Balsara, “Direct frequency modulation of an ADPLL for Bluetooth/GSM with injection pulling elimination,” IEEE Trans. on Circuits and Systems II, vol. 52, no. 6, pp. 339–343, June 2005.
K. Muhammad, T. Murphy, and R. B. Staszewski, “Verification of RF SoCs: RF, analog, baseband and software,” Proc. of 2006 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., sec. RTU1C-1, pp. 407–410, June 2006, San Francisco, CA.
R. B. Staszewski, K. Muhammad, and D. Leipold, “Digital RF Processor (DRPTM) for Cellular Phones,” Proc. of IEEE International Conf. on Computer Aided Design (ICCAD), pp. 122–129, Nov. 2005, San Jose, CA.
Y.-C. Ho, R. B. Staszewski, K. Muhammad, C.-M. Hung, D. Leipold, and K. Maggio, “Charge-domain signal processing of direct RF sampling mixer with discrete-time filters in Bluetooth and GSM receivers,” EURASIP Journal on Wireless Communications and Networking, vol. 2006, pp. Article ID 62905, 14 pages, 2006.
K. Muhammad and R. B. Staszewski, “Direct RF sampling mixer with recursive filtering in charge domain,” Proc. of 2004 IEEE Intl. Symp. on Circuits and Systems, sec. ASP-L29.5, pp. I-577–I-580, May 2004.
K. Muhammad, R. B. Staszewski, and C.-M. Hung, “Joint common mode voltage and differential offset voltage control scheme in a low-IF receiver,” Proc. of 2004 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., sec. TU3C-2, pp. 405–408, June 2004.
S. Karvonen, T. Riley, J. Kostamovaara, “A low noise quadrature subsampling mixer,” Proc. of IEEE Intl. Symp. on Circuits and Systems, pp. 790–793, 2001.
S. Lindfors, A. Parssinen and K. A Halonen, “A 3-V 230-MHz CMOS decimation subsampler” IEEE Trans. on Circuits and Systems II, vol. 50, no. 3, pp. 105–117, Mar. 2003.
R. Bagheri, A. Mirzaei, S. Chehrazi, M. Heidari, M. Lee, M Mikhemar, W. Tang, and A. Abidi, “An 800MHz to 5GHz software-defined radio receiver in 90nm CMOS,” Proc. of IEEE Solid-State Circuits Conf., sec. 26.6, pp. 480-481, 667, Feb. 2006.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2011 Springer Science+Business Media, LLC
About this chapter
Cite this chapter
Staszewski, R.B. (2011). Digital RF and Digitally-Assisted RF. In: Okada, K., Kousai, S. (eds) Digitally-Assisted Analog and RF CMOS Circuit Design for Software-Defined Radio. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-8514-9_3
Download citation
DOI: https://doi.org/10.1007/978-1-4419-8514-9_3
Published:
Publisher Name: Springer, New York, NY
Print ISBN: 978-1-4419-8513-2
Online ISBN: 978-1-4419-8514-9
eBook Packages: EngineeringEngineering (R0)