Skip to main content

Nanoscale CMOS Transceiver Implementation for a Software-Defined Radio Platform

  • Chapter
  • First Online:
Digitally-Assisted Analog and RF CMOS Circuit Design for Software-Defined Radio
  • 1679 Accesses

Abstract

A Software-Defined Radio (SDR) should theoretically receive and transmit any modulated frequency channel in the (un)licensed spectrum, targeting all modern communication standards relevant for a modern handheld mobile device (2G/3G/4G cellular, Wireless Local Area Networks (WLAN), Bluetooth, Global Positioning System (GPS), broadcasting, etc.). Moreover, it should guarantee top performance with energy savings, while still being integrated in a digital CMOS technology. In this chapter, a practical front-end implementation for such an SDR concept is demonstrated, including local oscillator, transmitter and receiver in the frequency range 0.1–6 GHz. Circuits and architectures are optimized for minimal area occupation in a standard digital 40 nm low-power (LP) CMOS technology. The radio front-end compares favorably with state-of-the-art dedicated radios while enabling, for the first time, wideband reconfigurable performance and energy scalability.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 149.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. L. Van der Perre, J. Craninckx, and A. Dejonghe, Green Software Defined Radios, Springer, 2009.

    Google Scholar 

  2. J. Mitola, “The Software Radio Architecture,” IEEE Commun. Mag., vol. 33, no. 5, pp. 26–38, May 1995.

    Article  Google Scholar 

  3. A. A. Abidi, “The Path to the Software-Defined Radio Receiver,” IEEE J. Solid-State Circuits, vol. 42, no. 5, pp. 954–966, May 2007.

    Article  Google Scholar 

  4. V. Giannini et al., “A 2mm2 0.1–5GHz Software-Defined Radio Receiver in 45-nm Digital CMOS”, IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3486–3498, Dec. 2009.

    Google Scholar 

  5. M. Ingels et al., “A 5mm2 40nm LP CMOS Transceiver for a Software-Defined Radio Platform”, IEEE J. Solid-State Circuits, vol. 45, no. 12, Dec. 2010.

    Google Scholar 

  6. V. Derudder et al., “A 200 Mbps + 2.14 nJ/b Digital Baseband Multi Processor System-on-Chip for SDRs,” in Symp. VLSI Circuits Dig. Tech. Papers, 2009, pp. 292–293.

    Google Scholar 

  7. GPP Technical Specification Group Radio Access Network, E-UTRA User Equipment (UE) radio transmission and reception (Release 8), “3GPP TS 36.101 V8.6.0 (2009–06)”.

    Google Scholar 

  8. J. Craninckx et al., “A Fully Reconfigurable Software-Defined Radio Transceiver in 0. 13 μm CMOS,” in IEEE ISSCC Dig. Tech. Papers, pp. 346–607, Feb. 2007

    Google Scholar 

  9. R. Bagheri et al., “An 800-MHz-6-GHz Software-Defined Wireless Receiver in 90-nm CMOS,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2860–2876, Dec. 2006.

    Article  Google Scholar 

  10. W. Eberle and M. Goffioul, “A Scalable Low-Power Digital Communication Network Architecture and an Automated Design Path for Controlling the Analog/RF Part of SDR Transceivers,” in Proc. Design, Automation and Test in Europe (DATE), Mar. 2008, pp. 710–715.

    Google Scholar 

  11. B. Debaillie, P. Van Wesemael, and J. Craninckx, “Calibration Method Enabling Low-Cost SDR,” in Proc. IEEE Int. Conf. Communications (ICC), 2008, pp. 4899–4903.

    Google Scholar 

  12. B. Debaillie, P. Van Wesemeal, and J. Craninckx, “Calibration of SDR Circuit Imperfections,” in Proc. IEEE Global Telecommunications Conf. (GLOBECOM), 2008, pp. 1–5.

    Google Scholar 

  13. J. Borremans, et al., “Low-Area Active-Feedback Low-Noise Amplifier Design in Scaled Digital CMOS”, IEEE J. Solid-State Circuits, vol. 43, no. 11, pp. 2422–2433, Nov. 2008.

    Article  Google Scholar 

  14. X. He and J. van Sinderen, “A Low-Power, Low-EVM, SAW-Less WCDMA Transmitter Using Direct Quadrature Voltage Modulation”, IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3448–3458, Dec. 2009.

    Article  Google Scholar 

  15. P. Nuzzo et al., “A 0.1–5GHz Dual-VCO software-defined ΣΔ frequency synthesizer in 45nm digital CMOS”, IEEE Radio Frequency Integrated Circuits Symposium (RFIC), pp. 321–324, June 2009.

    Google Scholar 

  16. A. Mazzanti and P. Andreani, “Class-C Harmonic CMOS VCOS, with a General Result on Phase Noise,” IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2716–2729, Dec. 2008.

    Article  Google Scholar 

  17. D. Hauspie, E.-C. Park, and J. Craninckx, “Wideband VCO with Simultaneous Switching of Frequency Band, Active Core, and Varactor Size,” IEEE J. Solid-State Circuits, vol. 42, no. 7, pp. 1472–1480, July 2007.

    Article  Google Scholar 

  18. C. S. Vaucher, et al., “A Family of Low-Power Truly Modular Programmable Dividers in Standard 0. 35 μm CMOS Technology,” IEEE J. Solid-State Circuits, vol. 35, no. 7, pp. 1039–1045, July 2000.

    Google Scholar 

  19. Y.-C. Yang, S.-A. Yu, Y.-H. Liu, T. Wang, and S.-S. Lu, “A Quantization Noise Suppression Technique for Delta Sigma Fractional-N Frequency Synthesizers,” IEEE J. Solid-State Circuits, vol. 41, no. 11, pp. 2500–2511, Nov. 2006.

    Article  Google Scholar 

  20. D. Kaczman et al., “A Single-Chip 10-Band WCDMA/HSDPA 4-Band GSM/EDGE SAW-less CMOS Receiver with DigRF 3G Interface and + 90 dBm IIP2”, IEEE J. Solid-State Circuits, vol. 44, no. 3, pp. 718–739, March 2009.

    Article  Google Scholar 

  21. S. Chehrazi et al.,“Second-Order Intermodulation in Current-Commutating Passive FET Mixers,” IEEE Transactions on Circuits and Systems I, vol. 56, no. 12, pp. 2556–2568, Dec. 2009.

    Article  MathSciNet  Google Scholar 

  22. I. Elahi et al., “IIP2 calibration by injecting DC offset at the mixer in a wireless receiver,” IEEE Trans. Circuits Syst., vol. 54, no. 12, pp.1135–1139, Dec. 2007.

    Article  Google Scholar 

  23. B. Debaillie, P. Van Wesemael, G. Vandersteen, J. Craninckx, “Calibration of Direct-Conversion Transceivers,” IEEE Journal of Selected Topics in Signal Processing, Vol. 3, pp. 488–498, 2009.

    Article  Google Scholar 

  24. V. Giannini, J. Craninckx, S. D’Amico and A. Baschirotto, “Flexible Baseband Analog Circuits for Software-Defined Radio Front-Ends”, IEEE J. Solid-State Circuits, vol. 42, no. 7, pp. 1501–1512, July 2007.

    Article  Google Scholar 

  25. P. Crombez, J. Craninckx, P. Wambacq, and M. Steyaert, “A 100-kHz to 20-MHz Reconfigurable Power-Linearity Optimized Gm-C Biquad in 0. 13 μm CMOS,” IEEE Trans. Circuits Syst. II: Expr. Briefs, vol. 55, no. 3, pp. 224–228, Mar. 2008.

    Google Scholar 

  26. J. Craninckx and G. Van der Plas, “A 65fJ/conversion-step 0-to-50MS/s 0-to-0.7mW 9b charge-sharing SAR ADC in 90nm digital CMOS,” in ISSCC Dig. Tech. Papers, pp. 246–247, Feb. 2007.

    Google Scholar 

  27. V. Giannini et al., “An 820 μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS”, ISSCC Dig. Tech. Papers, pp. 238–239, Feb. 2008.

    Google Scholar 

  28. M. Miyahara et al., “A low-noise self-calibrating dynamic comparator for high-speed ADCs,” in Proc. IEEE Asian Solid-State Circuits Conf., pp. 269–272, Nov. 2008.

    Google Scholar 

  29. C. Jones et al., “Direct-Conversion WCDMA Transmitter with -163dBc/Hz Noise at 190MHz Offset”, ISSCC Dig. Tech. Papers, pp. 336–337, Feb. 2007.

    Google Scholar 

  30. B. Leung, “VLSI for Wireless Communication”, ISBN 978–0138619985, Prentice Hall, 2002.

    Google Scholar 

  31. GSM Association, Official Document DG.09. “Battery Life Measurement Technique v5.1”, Sep. 2009.

    Google Scholar 

  32. ASITIC: Analysis and Simulation of Spiral Inductors and Transformers for ICs: http://rfic.eecs.berkeley.edu/~niknejad/asitic.html.

  33. I. Vassiliou et al., “A 65 nm CMOS multistandard, multiband TV tuner for mobile and multimedia applications”, IEEE J. Solid-State Circuits, vol. 43, no. 7, pp. 1522–1533, July 2008.

    Article  Google Scholar 

  34. K. Muhammad et al., “The first fully integrated quad-band GSM/GPRS receiver in a 90-nm digital CMOS process”, IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 1772–1783, Aug. 2006.

    Article  Google Scholar 

  35. Q. Huang et al., “A Tri-Band SAW-Less WCDMA/HSPA RF CMOS Transceiver with On-Chip DC-DC Converter Connectable to Battery”, in ISSCC Dig. Tech. Papers, pp. 60–61, Feb. 2010.

    Google Scholar 

  36. M. Gustafsson et al., “A Low Noise Figure 1.2-V CMOS GPS Receiver Integrated as a Part of a Multimode Receiver”, IEEE J. Solid-State Circuits, vol. 42, no. 7, pp. 1492–1500, July 2007.

    Google Scholar 

  37. L. Lin et al., “A fully integrated 2x2MIMO dual-band dual-mode direct-conversion CMOS transceiver for WiMAX/WLAN applications”, ISSCC Dig. Tech. Papers, pp. 202–607, Feb. 2009.

    Google Scholar 

  38. A. Behzad et al., “A fully integrated MIMO multiband direct conversion CMOS transceiver for WLAN applications (802.11 n)”, IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2795–2808, Dec. 2007.

    Google Scholar 

  39. M. Cassia et al., “A Low Power CMOS SAW-less Quad Band WCDMA/HSPA/1X/EGPRS Transmitter”, Proc. European Solid-State Circuits Conf. (ESSCIRC), pp. 146–149, Sept. 2008.

    Google Scholar 

  40. M. Cassia et al., “A Low-Power CMOS SAW-Less Quad Band WCDMA/HSPA/HSPA + /1X/EGPRS Transmitter”’, IEEE Journal of Solid-State Circuits, vol. 44, no. 7, pp. 1897–1906, July 2009.

    Article  Google Scholar 

  41. B. Tenbroek et al., “Single-Chip Tri-Band WCDMA/HSDPA Transceiver without External SAW Filters and with Integrated TX Power Control”, ISSCC Dig. Tech. Papers, pp. 202–203, Feb. 2008.

    Google Scholar 

  42. T. Sowlati et al., “Single-Chip Multiband WCDMA/HSDPA/HSUPA/EGPRS Transceiver with Diversity Receiver and 3G DigRF Interface without SAW Filters in Transmitter/3G Receiver Paths”, ISSCC Dig. Tech. Papers, pp. 116–117, Feb. 2009.

    Google Scholar 

Download references

Acknowledgment

The work presented here is the result of a large team effort, and the author would like to thank Jonathan Borremans, Björn Debaillie, Vito Giannini, Dries Hauspie, Mark Ingels, Gunjan Mandal, Pierluigi Nuzzo, Julien Ryckaert, Tomohiro Sano, Charlotte Soens, Joris Van Driessche, Peter Van Wesemael, Kameswaran Vengattaramane and Takaya Yamamoto for their contribution. This research has been carried out in the context of imec’s Green Radio Program and is partly sponsored by M4S, Panasonic, Renesas Electronics Corporation and Samsung.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Jan Craninckx .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2011 Springer Science+Business Media, LLC

About this chapter

Cite this chapter

Craninckx, J. (2011). Nanoscale CMOS Transceiver Implementation for a Software-Defined Radio Platform. In: Okada, K., Kousai, S. (eds) Digitally-Assisted Analog and RF CMOS Circuit Design for Software-Defined Radio. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-8514-9_2

Download citation

  • DOI: https://doi.org/10.1007/978-1-4419-8514-9_2

  • Published:

  • Publisher Name: Springer, New York, NY

  • Print ISBN: 978-1-4419-8513-2

  • Online ISBN: 978-1-4419-8514-9

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics