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Maximizing Power Supply Noise on Critical Paths

  • Mohammad Tehranipoor
  • Ke Peng
  • Krishnendu Chakrabarty
Chapter

Abstract

As technology scales, gate sensitivity to noise increases due to supply voltage scaling and limited scaling of the voltage threshold. As a result, power supply noise plays a greater role in sub-100 nm technologies and creates signal integrity issues in the chip. It is vital to consider supply voltage noise effects (1) during design validation to apply sufficient guardbands to critical paths and (2) during path delay test to ensure the performance and reliability of the chip. In this chapter, a layout-aware pattern generation procedure for maximizing power supply noise effects on critical paths while considering local voltage drop impacts is presented. The presented pattern generation and validation flow is implemented on the ITC’99 b19 benchmark. Experimental results for both wire-bond and flip-chip packaging styles are presented in this chapter. Results demonstrate that the presented method is fast, significantly increases switching around the functionally testable critical paths, and induces large voltage drop on cells placed in the critical paths which results in increased path delay. The presented method eliminates the very time consuming pattern validation phase that is practiced in industry.

References

  1. 1.
    A. H. Ajami, K. Banerjee, A. Mehrotra, and M. Pedram, “Analysis of IR-Drop Scaling with Implications for Deep Submicron P/G Network Designs” in Proc. of the Fourth International Symposium on Quality Electronic Design (ISQED’03), 2003, pp. 35–40Google Scholar
  2. 2.
    R. Saleh, S. Z. Hussain, S. Rochel, and D. Overhauser, “Clock skew verification in the presence of IR-Drop in the power distribution network,” in IEEE Trans. on Computer-Aided Design, vol. 19, No. 6, 2000, pp. 635–644Google Scholar
  3. 3.
    S. Pant, D. Blaauw, V. Zolotov, S. Sundareswaran, and R. Panda, “Vectorless Analysis of Supply Noise Induced Delay Variation,” in Proc. of the 2003 IEEE/ACM international conference on Computer-aided design, 2003, pp. 184–191Google Scholar
  4. 4.
    C. Tirumurti, S. Kundu, S. K. Susmita, and Y. S. Change “A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuits,” in Proc. of the Design, Automation and Test in Europe Conference, 2004, pp. 1078–1083Google Scholar
  5. 5.
    J. Wang, D. M. Walker, X. Lu, A. Majhi, B. Kruseman, G. Gronthoud, L. E. Villagra, P. J. A. M. van de Wiel, and S. Eichenberger, “ Modeling power supply noise in delay testing,” in IEEE Design & Test, vol. 24, issue 3, 2007, pp. 226–234Google Scholar
  6. 6.
    M. Nourani, M. Tehranipoor, and N. Ahmed, “Pattern Generation and Estimation for Power Supply Noise Analysis,” in Proc. of the 23rd IEEE VLSI Test Symposium, 2005, pp. 439–444Google Scholar
  7. 7.
    J. J. Liou, A. Krstic, Y. M. Jiang, and K. T. Cheng, “Path Selection and Pattern Generation for Dynamic Timing Analysis Considering Power Supply Noise Effects,” in Proc. of the 2000 IEEE/ACM international conference on Computer-aided design, 2000, pp. 493–497Google Scholar
  8. 8.
    A. Krstic, Y. M. Jiang, K. T. Cheng, “Pattern Generation for Delay Testing and Dynmaic Timing analysis Considering Power-Supply Noise Effects,” IEEE Transactions on CAD, vol. 20, No. 3, pp. 416–425, 2001Google Scholar
  9. 9.
    S. Zhao and K. Roy, “Estimation of Switching Noise on Power Supply Lines in Deep Sub-micro CMOS circuits,” in Proc. Thirteenth Int. Conf. on VLSI Design, pp. 168–173, 2000Google Scholar
  10. 10.
    http://crete.cadence.com, 0.18um standard cell GSCLib library version 2.0, Cadence, Inc., 2005

Copyright information

© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  • Mohammad Tehranipoor
    • 1
  • Ke Peng
    • 2
  • Krishnendu Chakrabarty
    • 3
  1. 1.ECE DepartmentUniversity of ConnecticutStorrsUSA
  2. 2.Freescale SemiconductorMicrocontroller Solutions GroupAustinUSA
  3. 3.ECE DepartmentDuke UniversityDurhamUSA

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