Maximizing Power Supply Noise on Critical Paths

  • Mohammad Tehranipoor
  • Ke Peng
  • Krishnendu Chakrabarty


As technology scales, gate sensitivity to noise increases due to supply voltage scaling and limited scaling of the voltage threshold. As a result, power supply noise plays a greater role in sub-100 nm technologies and creates signal integrity issues in the chip. It is vital to consider supply voltage noise effects (1) during design validation to apply sufficient guardbands to critical paths and (2) during path delay test to ensure the performance and reliability of the chip. In this chapter, a layout-aware pattern generation procedure for maximizing power supply noise effects on critical paths while considering local voltage drop impacts is presented. The presented pattern generation and validation flow is implemented on the ITC’99 b19 benchmark. Experimental results for both wire-bond and flip-chip packaging styles are presented in this chapter. Results demonstrate that the presented method is fast, significantly increases switching around the functionally testable critical paths, and induces large voltage drop on cells placed in the critical paths which results in increased path delay. The presented method eliminates the very time consuming pattern validation phase that is practiced in industry.


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Copyright information

© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  • Mohammad Tehranipoor
    • 1
  • Ke Peng
    • 2
  • Krishnendu Chakrabarty
    • 3
  1. 1.ECE DepartmentUniversity of ConnecticutStorrsUSA
  2. 2.Freescale SemiconductorMicrocontroller Solutions GroupAustinUSA
  3. 3.ECE DepartmentDuke UniversityDurhamUSA

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