SDD-Based Hybrid Method

  • Mohammad Tehranipoor
  • Ke Peng
  • Krishnendu Chakrabarty
Chapter

Abstract

Chapter 3 presented a SDF-based hybrid method to generate patterns with minimized pattern count and large long path sensitization. The pattern grading and selection is based on sensitized long paths of each test pattern in the original pattern repository. This method was enhanced in Chaps. 4 and 5. Chapter 4 is based on statistical timing analysis and takes process variations and crosstalk effects into consideration, when evaluating the sensitized path length. Chapter 5 enhances the hybrid method by taking the impacts of power supply noise and crosstalk into consideration when calculating the path delay. All these methods use sensitized long paths as a criteria to grade and select patterns, which makes them slow when scaling for large industry designs with millions of gates, due to the fact that the number of paths in the design increases exponentially with the circuit size [17, 18, 19].

References

  1. 1.
    David Salomon, “Data Compression, The Complete Reference, Forth Edition”, Springer Publishers, 2007Google Scholar
  2. 2.
    J. Geuzebroek, E.J. Marinissen, A. Majhi, A. Glowatz, F. Hapke, “Embedded multi-detect ATPG and Its Effect on the Detection of Unmodeled Defects”, in Proc. Int. Test Conference (ITC’07), pp. 1–10, 2007Google Scholar
  3. 3.
    J. Savir and S. Patil, “On Broad-Side Delay Test,” in Proc. VLSI 2 Symp. (VTS’94), pp. 284–290, 1994Google Scholar
  4. 4.
    R. Mattiuzzo, D. Appello C. Allsup, “Small Delay Defect Testing,” http://www.tmworld.com/article/CA6660051.html Test & Measurement World, 2009
  5. 5.
    Synopsys Inc., “TetraMAX ATPG, Automatic Test Pattern Generation,” Synopsys Datasheet, 2010Google Scholar
  6. 6.
    Mentor Graphics, “Tessent FastScan, Advanced Automatic Test Pattern Generation,” Silicon Test and Yield Analysis Datasheet, 2009Google Scholar
  7. 7.
    M. E. Amyeen, S. Venkataraman, A. Ojha, S. Lee, “Evaluation of the Quality of N-Detect Scan ATPG Patterns on a Processor”, IEEE International Test Conference (ITC’04), pp. 669–678, 2004Google Scholar
  8. 8.
    Y. Huang, “On N-Detect Pattern Set Optimization,” in Proc. IEEE the 7th Int. Symp. on Quality Electronic Design (ISQED’06), 2006Google Scholar
  9. 9.
    IWLS 2005 Benchmarks, “http://iwls.org/iwls2005/benchmarks.html
  10. 10.
    N. Ahmed, M. Tehranipoor and V. Jayaram, “Timing-Based Delay Test for Screening Small Delay Defects,” IEEE Design Automation Conf., pp. 320–325, 2006Google Scholar
  11. 11.
    A. K. Majhi, V. D. Agrawal, J. Jacob, L. M. Patnaik, “Line coverage of path delay faults,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 8, no. 5, pp. 610–614, 2000Google Scholar
  12. 12.
    H. Lee, S. Natarajan, S. Patil, I. Pomeranz, “Selecting High-Quality Delay Tests for Manufacturing Test and Debug,” in Proc. IEEE Int. Symp. on Defect and Fault-Tolerance in VLSI Systems (DFT’06), 2006Google Scholar
  13. 13.
    S. Goel, N. Devta-Prasanna and R. Turakhia, “Effective and Efficient Test pattern Generation for Small Delay Defects,” IEEE VLSI Test Symposium (VTS’09), 2009Google Scholar
  14. 14.
    S. Goel, K. Chakrabarty, M. Yilmaz, K. Peng, M. Tehranipoor, “Circuit Topology-Based Test Pattern Generation for Small-Delay Defects,” IEEE Asian Test Symposium (ATS’10), 2010Google Scholar
  15. 15.
    M. Yilmaz, K. Chakrabarty, and M. Tehranipoor, “Test-Pattern Grading and Pattern Selection for Small-Delay Defects,” in Proc. IEEE VLSI Test Symposium (VTS’08), 2008Google Scholar
  16. 16.
    M. Yilmaz, K. Chakrabarty, and M. Tehranipoor, “Interconnect-Aware and Layout-Oriented Test-Pattern Selection for Small-Delay Defects,” in Proc. Int. Test Conference (ITC’08), 2008Google Scholar
  17. 17.
    K. Peng, J. Thibodeau, M. Yilmaz, K. Chakrabarty, and M. Tehranipoor, “A Novel Hybrid Method for SDD Pattern Grading and Selection,” in Proc. IEEE VLSI Test Symposium (VTS’10), 2010Google Scholar
  18. 18.
    K. Peng, M. Yilmaz, K. Chakrabarty, and M. Tehranipoor, “A Noise-Aware Hybrid Method for SDD Pattern Grading and Selection,” Proc. IEEE Asian Test Symposium (ATS’10), 2010Google Scholar
  19. 19.
    K. Peng, M. Yilmaz, M. Tehranipoor, and K. Chakrabarty, “High-Quality Pattern Selection for Screening Small-Delay Defects Considering Process Variations and Crosstalk,” in Proc. IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE’10), 2010Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  • Mohammad Tehranipoor
    • 1
  • Ke Peng
    • 2
  • Krishnendu Chakrabarty
    • 3
  1. 1.ECE DepartmentUniversity of ConnecticutStorrsUSA
  2. 2.Freescale SemiconductorMicrocontroller Solutions GroupAustinUSA
  3. 3.ECE DepartmentDuke UniversityDurhamUSA

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