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Delay Test and Small-Delay Defects

  • Mohammad Tehranipoor
  • Ke Peng
  • Krishnendu Chakrabarty
Chapter

Abstract

As technology scales downwards, new challenges are emerging for test engineers. The deep-submicron effects are becoming more prominent with shrinking technology, thereby increasing the probability of timing-related defects [22, 24]. As a result, the stuck-at and I DDQ tests alone cannot ensure high quality level of chips, and at-speed test is needed to cover these timing-related defects. In the past, functional patterns were used for at-speed test. However, functional test generation is difficult and time-consuming for large complex designs. As mentioned previously, functional patterns also have pattern count and coverage issues. A cost-effective alternative are the scan-based structural tests generated by at-speed automatic test pattern generators. The transition fault model and path-delay fault model together provide relatively good coverage for delay-induced defects [5, 13, 26, 29].

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Copyright information

© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  • Mohammad Tehranipoor
    • 1
  • Ke Peng
    • 2
  • Krishnendu Chakrabarty
    • 3
  1. 1.ECE DepartmentUniversity of ConnecticutStorrsUSA
  2. 2.Freescale SemiconductorMicrocontroller Solutions GroupAustinUSA
  3. 3.ECE DepartmentDuke UniversityDurhamUSA

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