Diagnosing Noise-Induced SDDs by Using Dynamic SDF

  • Mohammad Tehranipoor
  • Ke Peng
  • Krishnendu Chakrabarty


Timing analysis is a very important step in validation of both an IC design’s performance and the quality of test patterns [2] used on that IC. There are many signal integrity (SI) issues in designs that may impact timing performance, often in the form of small-delay defects (SDDs), such as IR-drop and crosstalk effects. These SI issues are pattern-dependent parasitic effects that may significantly impact the design performance in the latest technologies.


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Copyright information

© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  • Mohammad Tehranipoor
    • 1
  • Ke Peng
    • 2
  • Krishnendu Chakrabarty
    • 3
  1. 1.ECE DepartmentUniversity of ConnecticutStorrsUSA
  2. 2.Freescale SemiconductorMicrocontroller Solutions GroupAustinUSA
  3. 3.ECE DepartmentDuke UniversityDurhamUSA

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