Advertisement

Introduction to VLSI Testing

  • Mohammad Tehranipoor
  • Ke Peng
  • Krishnendu Chakrabarty
Chapter

Abstract

Due to the complex mechanical and chemical steps involved in today’s manufacturing processes, inaccuracy and imperfections can be introduced to the fabricated chips or integrated circuits (ICs), and therefore they may not be able to perform exactly as the design specification intended. This may result in chip failures and profit loss. Therefore, testing is necessary to ensure that ICs operate correctly before being delivered to customers. Testing is a process used to identify ICs containing imperfections or manufacturing defects that may cause failures by applying test patterns to circuits and analyzing their responses. This book focuses on test for manufacturing and presents techniques and solutions for increasing the test quality for timing-related defect detection in integrated circuits.

References

  1. 1.
    A. Krstic and Kwang-Ting Cheng, “Delay Fault Test for VLSI Circuits”, Boston: Kluwer Academic Publishers, 1998Google Scholar
  2. 2.
    A. Krstic and Yi-Min Jiang and Kwang-Ting Cheng, “Delay testing considering power supply noise effects”, in IEEE International Test Conference (ITC’99), pp. 181–190, 1999Google Scholar
  3. 3.
    Cy Hay, “Testing Low Power Designs with Power-Aware Test, Manage Manufacturing Test Power Issues with DFTMAX and TetraMAX”, Synopsys White Paper, 2010Google Scholar
  4. 4.
    D. B. Armstrong, “A Deductive Method for Simulating Faults in Logic Circuits”, in IEEE Trans. on Computers, vol. C-21, no. 5, pp. 464–471, 1972Google Scholar
  5. 5.
    Dariusz Czysz, Grzegorz Mrugalski, Janusz Rajski, and Jerzy Tyszer, “Low Power Embedded Deterministic Test”, in 25th IEEE VLSI Test Symmposium (VTS’07), 2007Google Scholar
  6. 6.
    E. B. Eichelberger, E. Lindbloom, J. A. Waicukauski, and T. W. Williams, “Structured Logic Testing”, Englewood Cliffs, New Jersey: Prentice-Hall, 1991Google Scholar
  7. 7.
    E. G. Ulrich, V. D. Agrawal, and J. H. Arabian, “Concurrent and Comparative Discrete Event Simulation”, Boston: Kluwer Academic Publishers, 1994Google Scholar
  8. 8.
    H. Fujiwara, “FAN: A Fanout-Oriented Test Pattern Generation Algorithm”, in Proc. of the International Symp. on Circuits and Systems, pp. 671–674, 1985Google Scholar
  9. 9.
    H. Li and P. Shen and X. Li, “Robust test generation for precise crosstalk-induced path delay faults”, in Proc. VLSI 2 Symp. (VTS’06), 2006Google Scholar
  10. 10.
    J. A. Waicukauski, E. B. Eichelberger, D. O. Forlenza, E. Lindbloom, and T. McCarthy, “Fast Simulation for Structured VLSI”, in VLSI Systems Design, vol. 6, no. 12, pp. 20–32, 1985Google Scholar
  11. 11.
    J. Giraldi and M. L. Bushnell, “EST: The New Frontier in Automatic Test Pattern Generation”, in Proc. of the 27th Design Automation Conf., pp. 667–672, 1990Google Scholar
  12. 12.
    J. Giraldi and M. L. Bushnell, “Search State Equivalence for Redundancy Identification and Test Generation”, in Proc. of the International Test Conf., pp.184–193, 1991Google Scholar
  13. 13.
    J. P. Roth, “Diagnosis of Automata Failures: A Calculus and a Method”, in IBM Journal of Research and Development, vol. 10, no. 4, pp. 278–291, 1966Google Scholar
  14. 14.
    J. P. Roth, W. G. Bouricius, and P. R. Schneider, “Programmed Algorithms to Compute Tests to Detect and Distinguish Between Failures in Logic Circuits”, in IEEE Trans. on Electronic Computers, vol. EC-16, no. 5, pp. 567–580, 1967Google Scholar
  15. 15.
    J. Soden, and C. F. Hawkins, “IDDQ Testing: A Review”, in Journal of Electronic Testing: Theory and Applications (JETTA), vol. 3, no. 4, pp. 291–304, 1992Google Scholar
  16. 16.
    K. P. Parker, “The Boundary-Scan Handbook”, Boston: Kluwer Academic Publishers, second edition, 1998Google Scholar
  17. 17.
    L. Smith, “Model for Delay Faults Based upon Paths”, in IEEE International Test Conference (ITC’85), pp. 342–349, 1985Google Scholar
  18. 18.
    M. Abramovici, M. A. Breuer, and A. D. Friedman, “Digital Systems Testing and Testable Design”, Piscataway, New Jersey: IEEE Press, 1994. Revised printingGoogle Scholar
  19. 19.
    M. Bushnell and V. Agrawal, “Essentials of Electronics Testing for Digital Memory and Mixed-Signal VLSI Circuits”, ISBN 0-792-37991-8, Kluwer Publishers, 2000Google Scholar
  20. 20.
    M. H. Schulz and E. Auth, “Advanced Automatic Test Pattern Generation and Redundancy Identification Techniques”, in Proc. of the International Fault-Tolerant Computing Symp., pp. 30–35, 1988Google Scholar
  21. 21.
    M. H. Schulz and E. Auth, “Improved Deterministic Test Pattern Generation with Applications to Redundancy Identification”, in IEEE Trans. on Computer-Aided Design, vol. 8, no. 7, pp. 811–816, 1989Google Scholar
  22. 22.
    M. H. Schulz and E. Auth,, “SOCRATES: A Highly Efficient Automatic Test Pattern Generation System”, in IEEE Trans. on Computer-Aided Design, vol. CAD-7, no. 1, pp. 126–137, 1988Google Scholar
  23. 23.
    M. J. Y. Willaims and J. B. Angell, “Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic”, in IEEE Trans. on Computers, vol. C-22, no. 1, pp. 46–60, 1973Google Scholar
  24. 24.
    M. L. Bushnell and J. Giraldi, “A Functional Decomposition Method for Redundancy Identification and Test Generation”, in Journal of Electronic Testing: Theory and Applications, vol. 10, no. 3, pp. 175–195, 1997Google Scholar
  25. 25.
    M. Sachdev, “Defect Oriented Testing for CMOS Alalog and Digital Circuits”, ISBN:0-7923-8083-5, Boston: Kluwer Academic Publishers, 1998Google Scholar
  26. 26.
    Mentor Graphics, “Tessent TestKompress, ATPG with embedded compression”, in Silicon Test and Yield Analysis Datasheet, 2009Google Scholar
  27. 27.
    P. Goel, “An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits”, in Proc. of the International Fault-Tolerant Computing Symp., pp. 145–151, 1980Google Scholar
  28. 28.
    R. K. Gaede, M. R. Mercer, K. M. Butler, and D. E. Ross, “CATAPULT: Concurrent Automatic Testing Allowing Parallelization and Using Limited Topology”, in Proc. of the 25th Design Automation Conf., pp. 597–600, 1988Google Scholar
  29. 29.
    S. Seshu, “On an Improved Diagnosis Program”, in IEEE Trans. on Electronic Computers, vol. EC-14, no. 1, pp. 76–79, 1965Google Scholar
  30. 30.
    S. T. Chakradhar, V. D. Agrawal, and M. L. Bushnell, “Neural Models and Algorithms for Digital Testing”, Boston: Kluwer Academic Publishers, 1991Google Scholar
  31. 31.
    Srivaths Ravi, V. R. Devanathan, and Rubin Parekhji, “Methodology for Low Power Test Pattern Generation Using Activity Threshold Control Logic”, in Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design (ICCAD’07), 2007Google Scholar
  32. 32.
    T. Kirkland and M. R. Mercer, “A Topological Search Algorithm for ATPG”, in Proc. of the 24th Design Automation Conf., pp. 502–508, 1987Google Scholar
  33. 33.
    T. Stanion and D. Bhattacharya, “TSUNAMI: A Path Oriented Scheme for Algebraic Test Generation”, in Proc. of the International Fault-Tolerant Computing Symp., pp. 36–43, 1991Google Scholar
  34. 34.
    V. D. Agrawal, C. R. Kime, and K. K. Saluja, “A Tutorial on Built-In Self-Test, Part 2: Applications”, in IEEE Design & Test of Computers, vol. 10, no. 2, pp. 69–77, 1993Google Scholar
  35. 35.
    V. D. Agrawal, C. R. Kime, and K. K. Saluja, “Tutorial on Built-in Self-Test, Part 1: Principles”, in IEEE Design & Test of Computers, vol. 10, no. 1, pp. 73–82, Mar. 1993Google Scholar
  36. 36.
    V. R. Sar-Dessai and D. M. H. Walker, “Resistive bridge fault modeling, simulation and test generation”, in IEEE International Test Conference (ITC’99), pp. 596–605, 1999Google Scholar
  37. 37.
    W. Kunz and D. K. Pradhan, “Recursive Learning: A New Implication Technique for Efficient Solution to CAD Problems”, in IEEE Trans. on Computer-Aided Design, vol. 13, no. 9, pp. 1143–1158, 1994Google Scholar
  38. 38.
    W. Kunz and D. K. Pradhan, “Recursive Learning: An Attractive Alternative to the Decision Tree for Test Generation in Digital Circuits”, in Proc. of the International Test Conf., pp. 816–825, 1992Google Scholar
  39. 39.
    W. Kunz and D. Stoffel, “Reasoning in Boolean Networks: Logic Synthesis and Verification Using Testing Techniques”, Boston: Kluwer Academic Publishers, 1997Google Scholar
  40. 40.
    W.-T. Cheng and M.-L. Yu, “Differential Fault Simulation for Sequential Circuits”, in Journal of Electronic Testing: Theory and Applications, vol. 1, no. 1, pp. 7–13, 1990Google Scholar
  41. 41.
    M. Abramovici, P. R. Menon, and D. T. Miller, “Critical Path Tracing: An Alternative to Fault Simulation”, in IEEE Design & Test of Computers, vol. 1, no. 1, pp. 83–93, Feb. 1984Google Scholar
  42. 42.
    P. R. Menon, Y. H. Levendel, and M. Abramovici, “Critical Path Tracing in Sequential Circuits”, in Proc. of the International Conf. on Computer-Aided Design, Nov. 1988, pp. 162–165Google Scholar
  43. 43.
    S. K. Jain and V. D. Agrawal, “Statistical Fault Analysis”, in IEEE Design & Test of Computers, vol. 2, no. 1, pp. 38–44, Feb. 1985Google Scholar
  44. 44.
    J. Villoldo, P. Agrawal, and V. D. Agrawal, “STAFAN Algorithms for MOS Circuits”, in Proc. of the International Conf. on Computer Design, Oct. 1991, pp. 56–59Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  • Mohammad Tehranipoor
    • 1
  • Ke Peng
    • 2
  • Krishnendu Chakrabarty
    • 3
  1. 1.ECE DepartmentUniversity of ConnecticutStorrsUSA
  2. 2.Freescale SemiconductorMicrocontroller Solutions GroupAustinUSA
  3. 3.ECE DepartmentDuke UniversityDurhamUSA

Personalised recommendations