Predictable SDRAM Back-End

Abstract

Designing a predictable SDRAM controller is challenging. Traditional approaches are based on static scheduling of requests and SDRAM commands. This makes them unsuitable for many applications in contemporary System-on-Chips (SoCs), as they are getting increasingly input dependent and have diverse bandwidth and latency requirements. However, the timing constraints of SDRAM memories make it difficult to support dynamic behavior, since net bandwidth and latencies are traffic dependent and hard to bound at design time. This chapter starts with an overview of our predictable memory controller in Sect. 4.1 by discussing our decisions between static and dynamic arbitration and command generation, and between continuous and interleaved memory maps. The rest of this chapter focuses on the SDRAM back-end, saving the discussion about front-end arbitration for Chap. 5.