Combination of Redundancy and Error Correction

Part of the Integrated Circuits and Systems book series (ICIR)

The effects of redundancy and error checking and correction (ECC) are separately discussed in the previous chapters. However, more faults can be repaired by the combination of the redundancy and the ECC than by simply adding the effects of them. This synergistic effect, which was first reported in 1990 [1], is especially effective for repairing random-bit faults. Repairing many random-bit faults by redundancy is not effective. Since the replacement unit is usually a row or a column, bit faults require as many spare rows/columns except for the case of two or more bit faults located on the same row/column. On the contrary, ECC can potentially repair many random-bit faults. However, ECC using a single-error correction code can practically repair far fewer bit faults because the probability of “fault collision” (two or more faults being located in a code word) cannot be neglected as described in Sect. 3.6. By combining the redundancy and ECC, most bit faults are repaired by ECC and a few “fault collisions” are repaired by redundancy, resulting in dramatic increase of repairable faults [1–3].


  1. 1.
    H. L. Kalter, C. H. Stapper, J. E. Barth Jr., J. DiLorenzo, C. E. Drake, J. A. Fifield, G. A. Kelley Jr., S. C. Lewis, W. B. van der Hoeven and J. A. Yankosky, “A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC,” IEEE J. Solid-State Circuits, vol. 25, pp. 1118–1128, Oct. 1990.CrossRefGoogle Scholar
  2. 2.
    J. A. Fifield and C. H. Stapper, “High-speed on-chip ECC for synergistic fault-tolerant memory chips,” IEEE J. Solid-State Circuits, vol. 26, pp. 1449–1452, Oct. 1991.CrossRefGoogle Scholar
  3. 3.
    S.-H. Kim, W.-O. Lee, J.-H. Kim, S.-S. Lee, S.-Y. Hwang, C.-I. Kim, T.-W. Kwon, B.-S. Han, S.-K. Cho, D.-H. Kim, J.-K. Hong, M.-Y. Lee, S.-W. Yin, H.-G. Kim, J.-H. Ahn, Y.-T. Kim, Y.-H. Koh and J.-S. Kih, “A low power and high reliable 400Mbps mobile DDR SDRAM with on-chip distributed ECC,” in Proc. ASSCC, Nov. 2007, pp. 34–37.Google Scholar
  4. 4.
    C. H. Stapper and H.-S. Lee, “Synergistic fault-tolerance for memory chips,” IEEE Trans. Comput., vol. 41, pp. 1078–1087, Sep. 1992.CrossRefGoogle Scholar
  5. 5.
    M. Yamaoka, K. Osada, R. Tsuchiya, M. Horiuchi, S. Kimura and T. Kawahara, “Low power SRAM menu for SOC application using yin-yang-feedback memory cell technology,” in Symp. VLSI Circuits Dig. Tech. Papers, June 2004, pp. 288–291.Google Scholar
  6. 6.
    A. Agarwal, B. C. Paul and K. Roy, “Process variation in nano-scale memories: failure analysis and process tolerant architecture,” in Proc. CICC, Oct. 2004, pp. 353–356.Google Scholar
  7. 7.
    M. J. M. Pelgrom, A. C. J. Duinmaijer and A. P. G. Welbers, “Matching properties of MOS transistors,” IEEE J. Solid-State Circuits, vol. 24, pp. 1433–1440, Oct. 1989.CrossRefGoogle Scholar
  8. 8.
    Y. Taur, D. A. Buchanan, W. Chen, D. J. Frank, K. E. Ismail, S.-H. Lo, G. A. Sai-Halasz, R. G. Viswanathan, H.-J. C. Wann, S. J. Wind and H.-S. Wong, “CMOS scaling into the nanometer regime,” Proc. IEEE, vol. 85, pp. 486–504, Apr. 1997.CrossRefGoogle Scholar
  9. 9.
    K. Itoh, M. Horiguchi and M. Yamaoka, “Low-voltage limitations of memory-rich nano-scale CMOS LSIs,” in Proc. ESSCIRC, Sep. 2007, pp. 68–75.Google Scholar
  10. 10.
    K. Itoh, M. Horiguchi and H. Tanaka, Ultra-low voltage nano-scale memories, Springer, New York, 2007, Chapter 5.Google Scholar
  11. 11.
    K. Itoh and M. Horiguchi, “Low-voltage scaling limitations for nano-scale CMOS LSIs,” Solid-State Electron., vol. 53, pp. 402–410, Apr. 2009.CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  1. 1.Renesas Electronics CorporationTokyoJapan
  2. 2.Central Research LaboratoryHitachi Ltd.TokyoJapan

Personalised recommendations