Physical Analysis of NoC Topologies for 3-D Integrated Systems

Chapter
Part of the Integrated Circuits and Systems book series (ICIR)

Abstract

The manufacturing of integrated systems in multiple physical planes provides new opportunities for on-chip interconnection networks. Topologies of networks on-chip that have been of limited use due to the long and, therefore, slower interconnects can now be efficiently implemented in a vertically integrated circuit. Three-dimensional meshes are, reasonably, the first to be explored due to the simplicity of these topologies. Considerable improvements in delay and power can result from these topologies. These improvements originate either from the shorter interconnects or the decrease in the number of switches that data packets traverse to reach the destination network node. To evaluate the benefits obtained by a 3-D mesh on-chip network, appropriate latency and power models are described in this chapter. The accurate evaluation of the performance of these networks should be augmented by temperature-aware models that incorporate the power consumed by the processing elements of the network in addition to the power of the network links and switches. A methodology that includes these models is employed to determine the interconnect architecture within the PEs in each physical plane of a 3-D on-chip network.

References

  1. 1.
    G. De Micheli and L. Benini, Networks on Chips: Technology and Tools, Morgan Kaufmann, San Francisco, CA, 2006.Google Scholar
  2. 2.
    A. Jantsch and H. Tenhunen, Networks on Chip, Kluwer Academic, San Francisco, CA, 2003.Google Scholar
  3. 3.
    M. Millberg et al., “The Nostrum Backbone—A Communication Protocol Stack for Networks on Chip,” Proceedings of the IEEE International Conference on VLSI Design, pp. 693–696, January 2004.Google Scholar
  4. 4.
    J. M. Duato, S. Yalamanchili, and L. Ni, Interconnection Networks: An Engineering Approach, Morgan Kaufmann, San Francisco, CA, 2003.Google Scholar
  5. 5.
    D. Park et al., “MIRA: A Multi-Layered On-Chip Interconnect Router Architecture,” Proceedings of the IEEE International Symposium on Computer Architecture, pp. 251–261, June 2008.Google Scholar
  6. 6.
    C. Addo-Quaye, “Thermal-Aware Mapping and Placement for 3-D NoC Designs,” Proceedings of the IEEE International System-on-Chip Conference, pp. 25–28, September 2005.Google Scholar
  7. 7.
    F. Li et al., “Design and Management of 3D Chip Multiprocessors Using Network-in-Memory,” Proceedings of the IEEE International Symposium on Computer Architecture, pp. 130–142, June 2006.Google Scholar
  8. 8.
    V. F. Pavlidis and E. G. Friedman, “Three-Dimensional (3-D) Topologies for Networks-on-Chip,” Proceedings of the IEEE International System-on-Chip Conference, pp. 285–288, September 2006.Google Scholar
  9. 9.
    C. Seiculescu, S. Murali, L. Benini, and G. De Micheli, “SunFloor 3D: A tool for Networks on Chip Topology Synthesis for 3D Systems on Chips,” ACM/IEEE Design, Automation and Test in Europe Conference and Exhibition, pp. 9–14, April 2009.Google Scholar
  10. 10.
    W. J. Dally and B. Towles, Principles and Practices of Interconnection Networks, Morgan Kaufmann, San Francisco, CA, 2004.Google Scholar
  11. 11.
    L.-S. Peh and W. J. Dally, “A Delay Model for Router Microarchitectures,” IEEE Micro, Vol. 21, No. 1, pp. 26–34, January/February 2001.CrossRefGoogle Scholar
  12. 12.
    T. Sakurai, “Closed-Form Expressions for Interconnection Delay, Coupling, and Crosstalk in VLSI’s,” IEEE Transactions on Electron Devices, Vol. 40, No. 1, pp. 118–124, January 1993.CrossRefMathSciNetGoogle Scholar
  13. 13.
    K. A. Bowman et al., “A Physical Alpha-Power Law MOSFET Model,” IEEE Journal of Solid States Circuits, Vol. 34, No. 10, pp. 1410–1414, October 1999.CrossRefMathSciNetGoogle Scholar
  14. 14.
    S. L. Garverick and C. G. Sodini, “A Simple Model for Scaled MOS Transistors that Includes Field-Dependent Mobility,” IEEE Journal of Solid States Circuits, Vol. SC-22, No. 2, pp. 111–114, February 1987.CrossRefGoogle Scholar
  15. 15.
    The International Technology Roadmap for Semiconductors Reports, 2009 [Online]. Available: http://www.itrs.net/Links/2008ITRS/Home2008.htmGoogle Scholar
  16. 16.
    Predictive Technology Model [Online]. Available: http://www.eas.asu.edu/~ptmGoogle Scholar
  17. 17.
    W. Zhao and Y. Cao, “New Generation of Predictive Technology Model for Sub-45 nm Design Exploration,” Proceedings of the IEEE International Symposium on Quality Electronic Design, pp. 585–590, March 2006.Google Scholar
  18. 18.
    T. Sakurai and A. R. Newton, “Alpha-Power Law MOSFET Model and Its Applications to CMOS Inverter Delay and Other Formulas,” IEEE Journal of Solid State Circuits, Vol. 25, No. 2, pp. 584–594, April 1990.CrossRefGoogle Scholar
  19. 19.
    G. Chen and E. G. Friedman, “Low-Power Repeaters Driving RC and RLC Interconnects with Delay and Bandwidth Constraints,” IEEE Transactions on Very Large Integration (VLSI) Systems, Vol. 12, No. 2, pp. 161–172, February 2006.CrossRefGoogle Scholar
  20. 20.
    X. Xi et al., BSIM4 .5.0 MOSFET Model User’s Manual, University of California, Berkeley, CA, 2004.Google Scholar
  21. 21.
    H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison-Wesley, Reading, MA,1990.Google Scholar
  22. 22.
    Y. I. Ismail, E. G. Friedman, and J. L. Neves, “Equivalent Elmore Delay for RLC Trees,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 19, No. 1, pp. 83–97, January 2000.CrossRefGoogle Scholar
  23. 23.
    Y. I. Ismail, E. G. Friedman, and J. L. Neves, “Figures of Merit to Characterize the Importance of On-Chip Inductance,” IEEE Transactions on Very Large Integration (VLSI) Systems, Vol. 7, No. 4, pp. 442–449, December 1999.CrossRefGoogle Scholar
  24. 24.
    V. F. Pavlidis, I. Savidis, and E. G. Friedman, “Clock Distribution Networks for 3-D Integrated Circuits,” Proceedings of the IEEE International Conference on Custom Integrated Circuits, pp. 651–654, September 2008.Google Scholar
  25. 25.
    Massachusetts Institute of Technology Lincoln Laboratory, FDSOI Design Guide, Cambridge, 2006.Google Scholar
  26. 26.
    H. Hua et al., “Performance Trends in Three-Dimensional Integrated Circuits,” Proceedings of the International IEEE Interconnect Technology Conference, pp. 45–47, June 2006.Google Scholar
  27. 27.
    K. Banerjee and A. Mehrotra, “A Power-Optimal Repeater Insertion Methodology for Global Interconnects in Nanometer Design,” IEEE Transactions on Electron Devices, Vol. 49, No. 11, pp. 2001–2007, November 2002.CrossRefGoogle Scholar
  28. 28.
    H. J. M. Veendrick, “Short-Circuit Dissipation of Static CMOS Circuitry and Its Impact on the Design of Buffer Circuits,” IEEE Journal of Solid State Circuits, Vol. SC-19, No. 4, pp. 468–473, August 1984.CrossRefGoogle Scholar
  29. 29.
    K. Nose and T. Sakurai, “Analysis and Future Trend of Short-Circuit Power,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 19, No. 9, pp. 1023–1030, September 2000.CrossRefGoogle Scholar
  30. 30.
    G. Chen and E. G. Friedman, “Effective Capacitance of Inductive Interconnects for Short-Circuit Power Analysis,” IEEE Transactions on Circuits and Systems I: Brief Papers, Vol. 55, No. 1, pp. 26–30, January 2008.Google Scholar
  31. 31.
    P. R. O’Brien and T. L. Savarino, “Modeling the Driving-Point Characteristic of Resistive Interconnect for Accurate Delay Estimation,” Proceedings of the International IEEE/ACM Conference on Computer-Aided Design, pp. 512–515, April 1989.Google Scholar
  32. 32.
    H. Wang, L.-S. Peh, and S. Malik, “Power-Driven Design of Router Microarchitectures in On-Chip Networks,” Proceedings of the IEEE International Symposium on Microarchitecture, pp. 105–116, December 2003.Google Scholar
  33. 33.
    V. F. Pavlidis and E. G. Friedman, Three-Dimensional Integrated Circuit Design, Morgan Kaufmann, San Francisco, CA, 2009.Google Scholar
  34. 34.
    V. F. Pavlidis and E. G. Friedman, “Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits,” Proceedings of the IEEE, Special Issue on 3-D Integration Technology, Vol. 97, No. 1, pp. 123–140, January 2009.Google Scholar
  35. 35.
    J. W. Joyner and J. D. Meindl, “Opportunities for Reduced Power Distribution Using Three-Dimensional Integration,” Proceedings of the IEEE International Interconnect Technology Conference, pp. 148–150, June 2002.Google Scholar
  36. 36.
    J. W. Joyner et al., “Impact of Three-Dimensional Architectures on Interconnects in Gigascale Integration,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 9, No. 6, pp. 922–927, December 2000.CrossRefGoogle Scholar
  37. 37.
    R. Venkatesan, J. A. Davis, K. A. Bowman, and J. D. Meindl, “Optimal n-tier Multilevel Interconnect Architectures for Gigascale Integration (GSI),” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 9, No. 6, pp. 899–912, December 2001.CrossRefGoogle Scholar
  38. 38.
    T.-Y. Chiang, S. J. Souri, C. O. Chui, and K. C. Saraswat, “Thermal Analysis of Heterogeneous 3D ICs with Various Integration Scenarios,” Proceedings of the IEEE International Electron Device Meeting, pp. 681–684, December 2001.Google Scholar
  39. 39.
    T.-Y. Chiang, K. Banerjee, and K. C. Saraswat, “Analytical Thermal Model for Multilevel VLSI Interconnects Incorporating Via Effect,” IEEE Electron Device Letters, Vol. 23, No. 1, pp. 31–33, January 2002.CrossRefGoogle Scholar
  40. 40.
    C. Marcon et al., “Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique,” Proceedings of the ACM/IEEE Design, Automation and Test in Europe Conference and Exhibition, Vol. 1, pp. 502–507, March 2005.Google Scholar
  41. 41.
    P. P. Pande et al., “Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures,” IEEE Transactions on Computers, Vol. 54, No. 8, pp. 1025–1039, August 2005.CrossRefGoogle Scholar
  42. 42.
    X. Zhao, D. L. Lewis, H.-S. H. Lee, and S. K. Lim, “Pre-Bond Testable Low-Power Clock Tree Design for 3D Stacked ICs,” Proceedings of the IEEE/ACM International Conference on Computer Aided Design, pp. 184–190, November 2009.Google Scholar
  43. 43.
    V. F. Pavlidis and E. G. Friedman, “3-D Topologies for Networks-on-Chip,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 15, No. 10, pp. 1081–1090, October 2007.CrossRefGoogle Scholar
  44. 44.
    A. H. Ajami, K. Banerjee, and M. Pedram, “Modeling and Analysis of Nonuniform Substrate Temperature Effects on Global ULSI Interconnects,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 6, pp. 849–861, June 2005.CrossRefGoogle Scholar
  45. 45.
    J. C. Ku and Y. Ismail, “Thermal-Aware Methodology for Repeater Insertion in Low-Power VLSI Circuit,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 15, No. 8, pp. 963–970, August 2007.CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  1. 1.Integrated Systems Laboratory, EPFLLausanneSwitzerland
  2. 2.University of RochesterRochesterUSA

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