Skip to main content

Deterministic Test Generation Algorithms

  • Chapter
  • First Online:
  • 2460 Accesses

Abstract

The previous chapter provided an understanding of test generation and showed where and how test generation is used in digital system testing.

This is a preview of subscription content, log in via an institution.

Buying options

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   69.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   89.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD   119.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

References

  1. Roth JP (1966) Diagnosis of automata failures: a calculus and a method. IBM J Res Dev 10(4):278–291

    Article  Google Scholar 

  2. Roth JP, Bouricius WG, Schneider PR (1967) Programmed algorithms to compute tests to detect and distinguish between failures in logic circuits. IEEE Trans Electron Comput EC-16(5):567–580

    Article  Google Scholar 

  3. Goel P (1981) An implicit enumeration algorithm to generate tests for combinational logic circuits. IEEE Trans Comput C-30(3):215–222

    Article  Google Scholar 

  4. Fujiwara H (1985) FAN: A Fanout-oriented test pattern generation algorithm. In: Proceedings of the international symposium on circuits and systems, pp 671–674, July 1985

    Google Scholar 

  5. Fujiwara H, Shimono T (1983) On the acceleration of test generation algorithms. In: Proceedings of the international fault-tolerant computing symposium, pp 98–105, June 1983

    Google Scholar 

  6. Fujiwara H, Shimono T (1983) On the acceleration of test generation algorithms. IEEE Trans Comput C-32(12):1137–1144

    Article  Google Scholar 

  7. Schulz MH, Auth E (1988) Advanced automatic test pattern generation and redundancy identification techniques. In: Proceedings of the international fault-tolerant computing symposium, pp 30–35, June 1988

    Google Scholar 

  8. Schulz MH, Auth E (1989) Improved deterministic test pattern generation with applications to redundancy identification. IEEE Trans Comput-Aided Des 8(7):811–816

    Article  Google Scholar 

  9. Schulz MH,Trischler E, Serfert TM (1988) SOCRATES: A highly efficient automatic test pattern generation system. IEEE Trans Comput-Aid Des CAD-7(1):126–137

    Article  Google Scholar 

  10. Abramovici M, Breuer MA, Friedman AD (1994) Digital systems testing and testable design. IEEE Press, Piscataway, NJ. Revised printing

    Book  Google Scholar 

  11. Abramovici M, Menon PR, Miller DT (1984) Critical path tracing: an alternative to fault simulation. IEEE Des Test Comput 1(1):83–93

    Article  Google Scholar 

  12. Menon PR,Levendel YH, Abramovici M (1988) Critical path tracing in sequential circuits. In: Proceedings of the international conference on computer-aided design, pp 162–165, Nov. 1988

    Google Scholar 

  13. Menon PR,Levendel YH, Abramovici M (1991) SCRIPT: A critical path tracing algorithm for synchronous sequential circuits. IEEE Trans Comput-Aided Des 10(6):738–747

    Article  Google Scholar 

  14. Bushnell ML, Agrawal VD (2000) Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits. Kluwer, Dordecht

    Google Scholar 

  15. Miczo A (2003) Digital logic testing and simulation, 2nd Ed. Wiley, New York

    Book  Google Scholar 

  16. Jha N, Gupta S (2003) Testing of digital systems. Cambridge University Press, Cambridge

    Book  Google Scholar 

  17. Pomeranz I, Reddy SM (1996) On static compaction of test sequences for synchronous sequential circuits. Proceedings of third design automation conference, pp 215–220

    Google Scholar 

  18. Nsiao MS, Rudnick EM, Patel JH (1997) Fast algorithms for static compaction of sequential circuit test vector. Proceedings of 15th IEEE VLSI test symposium, pp. 188–195

    Google Scholar 

  19. Hamzaoglu I, Patel JH (2000) Test set compaction algorithm for combinational circuits. IEEE Trans Comput Aided Des Integr Circuits Syst 19(8):957–963

    Article  Google Scholar 

  20. Rudnick EM, Patl JH (1996) Simulation based techniques for dynamic test sequence compaction. IEEE/ACM international conference on computer aided design, pp 67–73

    Google Scholar 

  21. Niermann TM,Roy RK,Patel JH, Abraham JA (1992) Test compaction for sequential circuits. IEEE Trans Comput Aided Des Integr Circuits Syst 11(2):260–267

    Article  Google Scholar 

  22. Goel P, Rosales BC (1979) Test generation and dynamic compaction of tests. Proceedings of test conference, pp 189–192

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Zainalabedin Navabi .

Rights and permissions

Reprints and permissions

Copyright information

© 2011 Springer Science+Business Media, LLC

About this chapter

Cite this chapter

Navabi, Z. (2011). Deterministic Test Generation Algorithms. In: Digital System Test and Testable Design. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-7548-5_6

Download citation

  • DOI: https://doi.org/10.1007/978-1-4419-7548-5_6

  • Published:

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4419-7547-8

  • Online ISBN: 978-1-4419-7548-5

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics