Test Pattern Generation Methods and Algorithms



Test vectors are generated for post manufacturing test of a digital system. Because of the complexity of digital systems, the size of necessary tests, and test quality factors, automatic methods are used for generation of test patterns. This process is referred to as automatic test pattern generation (ATPG). For a circuit under test (CUT), test pattern generation must be due to the testing of the circuit as thoroughly as possible, and in the shortest possible time.


Test Generation Random Test Test Vector Primary Input Fault Coverage 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 1.
    Sellers FF, Hsiao MY, Bearnson LW (1968) Analyzing errors with the Boolean difference. IEEE Trans Comput C-17(7):676–683.CrossRefGoogle Scholar
  2. 2.
    Akers SB (1959) On a theory of Boolean functions. J. SIAM 7.Google Scholar
  3. 3.
    Sellers FF Jr., Hsiao M-Y, Bearnson LW (1968) Error detecting logic for digital computers. New York: McGraw-Hill.Google Scholar
  4. 4.
    Agrawal P, Agrawal VD (1975) Probabilistic analysis of random test generation method for Irredundant Combinational Logic Networks. IEEE Trans Comput C-24(7):691–695.CrossRefGoogle Scholar
  5. 5.
    Agrawal P, Agrawal VD (1976) On Monte Carlo testing of logic tree networks. IEEE Trans Comput C-25(6):664–667.CrossRefGoogle Scholar
  6. 6.
    Agrawal VD (1978) When to use random testing. IEEE Trans Comput C-27(11):1054–1055.CrossRefGoogle Scholar
  7. 7.
    Parker KP, McCluskey EJ (1975) Probabilistic treatment of general combinational networks. IEEE Trans Comput C-24(6):668–670.CrossRefGoogle Scholar
  8. 8.
    Eichelberger EB, Lindbloom E (1983) Random-pattern coverage enhancement and diagnosis for LSSD logic self-test. IBM J Res Dev 27(3):265–272.CrossRefGoogle Scholar
  9. 9.
    Goldstein LH (1979) Controllability/observability analysis of digital circuits. IEEE Trans Circuits Syst CAS-26(9):685–693.CrossRefGoogle Scholar
  10. 10.
    Rutman RA (1972) Fault-detection test generation for sequential logic by Heuristic Tree Search. Technical Report TP-72-11-4, U. of Southern California, Dept. of EESystems, Los Angeles, California.Google Scholar
  11. 11.
    Agrawal VD, Mercer MR (1982) Testability measures – what do they tell us? in Proceedings of the International Test Conference. 391–396 Nov. 1982Google Scholar
  12. 12.
    Savir J (1983) Good controllability and good observability do not guarantee good testability. IEEE Trans Comput, C-32:1198–1200.CrossRefGoogle Scholar
  13. 13.
    Jain SK, Agrawal VD (1985) Statistical fault analysis. IEEE Design Test Comput 2(1):38–44.CrossRefGoogle Scholar
  14. 14.
    Brglez F (1984) On testability analysis of combinational networks. in Proceedings of the International Symposium on Circuits and Systems, 221–225 May 1984Google Scholar
  15. 15.
    Grason J (1979) TMEAS A testability measurement. Program. Proceedings 16th Design Automation Conference 156–161 June, 1979Google Scholar
  16. 16.
    Goldstein LH, Thigpen EL (1980) SCOAP: Sandia controllability/observability analysis program, in proceedings of the 17th Design Automation Conference, 190–196 June 1980Google Scholar
  17. 17.
    Bushnell ML, Agrawal VD (2000) Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits, Kluwer Academic PublishersGoogle Scholar
  18. 18.
    Wang L-T, Wu C-W, Wen X VLSI Test Principles and Architectures: Design for Testability, Morgan Kaufmann, July 2006.Google Scholar

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© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  1. 1.Department of Electrical & Computer EngineeringWorcester Polytechnic InstituteWorcesterUSA

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