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Low-Power and Variation-Tolerant Memory Design

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Low-Power Variation-Tolerant Design in Nanometer Silicon

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Abstract

This chapter discusses the impact of process variations on reliability of Static Random Access Memory (SRAM). An overview of SRAM and process variations in the context of SRAM is provided. The mechanisms of SRAM parametric failures are discussed. Models and methods of estimating parametric yield of SRAM array and failure probabilities of SRAM cell under process variations are presented. Design approaches for enhancing the yield of SRAM under process variations are discussed. The design approaches discussed include statistical joint optimization of SRAM cell sizing and redundancy, dynamic circuit techniques, post silicon adaptive repair techniques, and variation-tolerant SRAM peripherals. A self-repairing SRAM is discussed which adaptively adjusts its body bias to improve its reliability. Finally, a discussion on adaptive low-power and variation-tolerant SRAM design for multi-media applications is provided.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, San Francisco State University, San Francisco, CA, USA

    Hamid Mahmoodi

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  1. Hamid Mahmoodi
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Correspondence to Hamid Mahmoodi .

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Editors and Affiliations

  1. Dept. Electrical Engineering &, Computer Science, Case Western Reserve University, Euclid Avenue 10900, Cleveland, 44106-7071, Ohio, USA

    Swarup Bhunia

  2. School of Electrical &, Computer Engineering, Georgia Institute of Technology, Ferst Drive 266, Atlanta, 30332-0250, Georgia, USA

    Saibal Mukhopadhyay

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Mahmoodi, H. (2011). Low-Power and Variation-Tolerant Memory Design. In: Bhunia, S., Mukhopadhyay, S. (eds) Low-Power Variation-Tolerant Design in Nanometer Silicon. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-7418-1_5

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  • DOI: https://doi.org/10.1007/978-1-4419-7418-1_5

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