RISPP Architecture Details
The novel modular special instructions (SIs) are described in Chap. 3 and the novel run-time system that dynamically determines the reconfiguration decisions to exploit the features of modular SIs is described in Chap. 4. To implement modular SIs, connect them to the core pipeline, and allow a run-time system to determine reconfiguration decision, a specialized processor architecture is needed to support these features, i.e., the RISPP architecture. In Sect. 4.1 and, in particular, in Fig. 4.1, a first overview of the RISPP architecture is given. There, it was already pointed out that it is not intended to define a completely new processor architecture. Instead, RISPP builds upon an existing architecture that is extended toward the RISPP requirements. In particular, in the scope of the presented work, a DLX core processor (created with ASIP Meister [ASI]) and later a SPARC V8 core processor (Leon2 [Aer]) were examined. This chapter focuses on the implementation details of the Leon2 prototype, although the general concepts are applicable to other architectures as well.