Abstract
Selection of a good memory architecture is a crucial step during embedded system design, since it heavily influences the required chip size, achievable throughput, and occurring power dissipation. This is particularly true in case of image processing applications because of the huge amounts of data that have to be processed.
Reference [109], for instance, reports that clock distribution and memory belong to the most energy-consuming parts of a typical ASIC. In case of a digital audio broadcast (DAB) chip, memory contributes to 66% of the global power dissipation [140]. Similar values are reported for an H.264/AVC core [201], where SRAM has been responsible for 70% of the energy requirements. Usage of external RAM is even more expensive due to the necessary energy-consuming driver circuits. Consequently, the memory subsystem typically accounts for 50–80% of the power consumption [291, 305, 59]. One possibility to limit these power requirements consists in trying to reduce the amount of required buffer size, since individual memory accesses become more expensive with increasing capacities [60, 245, 17, 109, 59]. Essentially, this can be explained by the leakage power of each individual memory cell as well as by the row decoding [109].
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Notes
- 1.
\(4096\times2160\times3\times12 \ bit\), assuming three components and 12 bit precision.
- 2.
The relation \(\theta:\mathbf{I}\mapsto\mathbf{i}\) can be considered as a so-called multidimensional schedule .
- 3.
Note: \(\langle\Delta\mathbf{g},\mathbf{e_{1}}\rangle=\infty\).
References
Azizi-Mazreah, A., Manzuri-Shalmani, M.T., Barati, H., Barati, A.: Delay and energy consumption analysis of conventional SRAM. In: Proceedings of World Academy of Science, Engineering and Technology, vol. 27, pp. 35–39. Paris, France (2008)
Catthoor, F., Franssen, F., Wuytack, S., Nachtergaele, L., De Man, H.: Global communication and memory optimizing transformations for low power signal processing systems. In: Workshop on VLSI Signal Processing VII, pp. 178–187. IEEE Press, La Jolla, CA (1994)
Catthoor, F., Wuytack, S., Greef, E.D., Balasa, F., Nachtergaele, L., Vandecappelle, A.: Custom Memory Management Methodology – Exploration of Memory Organisation for Embedded Multimedia System Design. Kluwer, Boston, MA (1998)
Darte, A., Schreiber, R., Villard, G.: Lattice-based memory allocation. Tech. Rep. RR2004-23, ENS-Lyon (2004)
GadelRab, S., Bond, D., Reynolds, D.: Fight the power – power reduction ideas for ASIC designers and tool providers. Tech. Rep., Tundra Semiconductor Corporation 603 March Road, Ottawa, Ontario, K2K 2M5, Canada (2005)
Hu, Q.: Hierarchical memory size estimation for loop transformation and data memory platform optimization. Ph.D. thesis, Norwegian University of Science and Technology, Faculty of Information Technology, Mathematics and Electrical Engineering, Department of Electronics and Telecommunications (2007)
Lefebvre, V.: Restructuration automatique des variables d’un programme en vue de sa parallélilsation. Ph.D. thesis, Université de Versailles (1998)
Liu, T.M., Chung, C.C., Lee, C.Y., Lin, T.A., Wang, S.Z.: Design of a 125μw, fully-scalable MPEG-2 and H.264/AVC video decoder for mobile applications. In: Proceedings of the 43rd Annual Conference on Design Automation (DAC ’06), pp. 288–289. ACM Press, New York, NY (2006)
Porter, R.B.: Image processing algorithms and architectures for reconfigurable computers. In: Reconfigurable Computing: Accelerating Computation with Field-Programmable Gate Arrays. Springer, New York, NY (2005)
Ramanujam, J., Hong, J., Kandemir, M., Narayan, A.: Reducing memory requirements of nested loops for embedded systems. In: Proceedings of the 38th Conference on Design Automation (DAC ’01), pp. 359–364. ACM Press, New York, NY (2001)
Verdoolaege, S., Bruynooghe, M., Janssens, G., Catthoor, F.: Multi-dimensional incremental loop fusion for data locality. In: Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors, pp. 17–27. The Hague, The Netherlands (2003)
Wuytack, S., Catthoor, F., Nachtergaele, L., De Man, H.: Power exploration for data dominated video applications. Int. Symp. Low Power Electron. Des. pp. 359–364 (1996). DOI 10.1109/LPE.1996.547539
Zissulescu, C., Turjan, A., Kienhuis, B., Deprettere, E.: Solving out of order communication using CAM memory; an implementation. In: 13th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2002). Veldhoven, Netherlands (2002)
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Keinert, J., Teich, J. (2011). Memory Mapping Functions for Efficient Implementation of WDF Edges. In: Design of Image Processing Embedded Systems Using Multidimensional Data Flow. Embedded Systems. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-7182-1_6
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