Memory Mapping Functions for Efficient Implementation of WDF Edges

Abstract

Selection of a good memory architecture is a crucial step during embedded system design, since it heavily influences the required chip size, achievable throughput, and occurring power dissipation. This is particularly true in case of image processing applications because of the huge amounts of data that have to be processed.

Reference [109], for instance, reports that clock distribution and memory belong to the most energy-consuming parts of a typical ASIC. In case of a digital audio broadcast (DAB) chip, memory contributes to 66% of the global power dissipation [140]. Similar values are reported for an H.264/AVC core [201], where SRAM has been responsible for 70% of the energy requirements. Usage of external RAM is even more expensive due to the necessary energy-consuming driver circuits. Consequently, the memory subsystem typically accounts for 50–80% of the power consumption [291, 305, 59]. One possibility to limit these power requirements consists in trying to reduce the amount of required buffer size, since individual memory accesses become more expensive with increasing capacities [60, 245, 17, 109, 59]. Essentially, this can be explained by the leakage power of each individual memory cell as well as by the row decoding [109].