Circuit-Level Soft-Error Mitigation

Part of the Frontiers in Electronic Testing book series (FRET, volume 41)


In nanometric technologies, circuits are increasingly sensitive to various kinds of perturbations. Soft errors, a concern in the past for space applications, became a reliability issue at ground level. Alpha particles and atmospheric neutrons induce single-event upsets (SEUs) affecting memory cells, latches, and flip-flops, and single-event transients (SETs) initiated in the combinational logic and captured by the associated latches and flip-flops. To face this challenge, a designer must dispose a variety of soft-error mitigation schemes adapted to various circuit structures, design architectures, and design constraints. In this chapter, we describe several SEU and SET mitigation schemes that could help designers to meet their reliability constraints.


Clock Cycle Error Correct Code Soft Error Linear Feedback Shift Register Transient Fault 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  1. 1.TIMA Laboratory (CNRS, Grenoble INP, UJF)GrenobleFrance

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