Integrated Circuit Qualification for Space and Ground-Level Applications: Accelerated Tests and Error-Rate Predictions
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Integrated circuits (analog, digital or mixed) sensitivity evaluation to Single Event Effects (SEE) requires specific methodologies and dedicated tools. Indeed, such evaluation is based on data gathered from on-line tests performed in a suitable facility (cyclotron, linear accelerator, laser , etc.). The target circuit is exposed to particles fluxes having features (energy and range in Silicon) somewhat representative of the ones the circuit will encounter in its final environment. This chapter will describe and illustrate with experimental results, the methodologies and the hardware and software developments required for the evaluation of the sensitivity to SEE of integrated circuits. Those techniques will be applied to a SRAM-based FPGA and to a complex processor. In case of sequential circuits such as processors, the sensitivity to SEE will strongly depend on the executed program. Hardware/software fault-injection experiments, performed either on the circuit or on an available model, are proved as being complementary of radiation ground testing. Indeed, data issued from fault injection combined with data issued from radiation ground testing allow in accurately predicting the error rate of any program.
KeywordsFault Injection Soft Error Device Under Test Single Event Upset Single Event Effect
The authors would like to thank Robert Ecoffet and Michel Pignol from CNES for their significant contribution to these researches started in 1989 and Guy Berger, responsible of the HIF cyclotron where experiments were conducted, who offered a continuous support to this work.
They thank also Dominique Bellin, from e2v, and IROC Company who significantly contributed to the application of the test methods and tools developed at TIMA for the Power PC processor in the frame of the SCADRI project if Rhône-Alpes aeronautics & space Cluster.
Finally, the authors thank Joseph Foucard for his help in the redaction of this chapter.
- 2.T. Ma, P. Dressendorfer, “Ionizing Radiation Effects in MOS Devices and Circuits”, Wiley Eds., New York, 1989.Google Scholar
- 3.F. Faccio, “Design Hardening Methodologies for ASICs”, Radiation Effects on Embedded Systems, ISBN-10 1-4020-5645-1, Springer, 2007.Google Scholar
- 5.Bezerra F. et al, “Commercial Processor Single Event Tests”, 1997 RADECS Conference Data Workshop Record, pp. 41–46.Google Scholar
- 8.S. Duzellier, G. Berger, “Test Facilities for SEE and Dose Testing”, Radiation Effects on Embedded Systems, ISBN-10 1-4020-5645-1, Springer, 2007.Google Scholar
- 9.JEDEC standard, “Measurement and Reporting of Alpha particles and Terrestrial Cosmic Ray-Induced Soft Errors in Semiconductor Devices”, JESD89 Aug. 2001.Google Scholar
- 10.F. Faure, P. Peronnard, R. Velazco, “Thesic+: A flexible system for see testing”, In Proceedings of RADECS, 2002.Google Scholar
- 11.R. Velazco, P. Cheynet, A. Bofill, R. Ecoffet, “THESIC: A testbed suitable for the qualification of integrated circuits devoted to operate in harsh environment”, In Proceedings of IEEE European Test Workshop, pp. 89–90, 1998.Google Scholar
- 12.Gregory R. Allen, Gary M. Swift, “Single Event Effects Test Results for Advanced Field Programmable Gate Arrays”, IEEE Radiation Effects Data Workshop, July 2006.Google Scholar
- 13.C. Yui, G. Swift, C. Carmichael, “Single Event Upset Susceptibility Testing of the Xilinx Virtex II FPGA”, MAPLD, 2002.Google Scholar
- 16.A. Lesea, “Continuing Experiments of Atmospheric Neutron Effects on Deep Submicron Integrated Circuits”, Xilinx WP286, March 10, 2008.Google Scholar