Hardware Fault Injection

Part of the Frontiers in Electronic Testing book series (FRET, volume 41)


Hardware fault injection is the widely accepted approach to evaluate the behavior of a circuit in the presence of faults. Thus, it plays a key role in the design of robust circuits. This chapter presents a comprehensive review of hardware fault injection techniques, including physical and logical approaches. The implementation of effective fault injection systems is also analyzed. Particular emphasis is made on the recently developed emulation-based techniques, which can provide large flexibility along with unprecedented levels of performance. These capabilities provide a way to tackle reliability evaluation of complex circuits.


Clock Cycle Fault Injection Soft Error Device Under Test Fault Classification 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 1.
    R. C. Baumann, “Radiation-Induced Soft Errors in Advanced Semiconductor Technologies”, IEEE Transactions on Device and Materials Reliability, Vol. 5, No. 3, pp. 305–316, September 2005.MathSciNetCrossRefGoogle Scholar
  2. 2.
    J. Karlsson, P. Liden, P. Dalgren, R. Johansson, U. Gunnelfo, “Using Heavy-Ion Radiation to Validate Fault Handling Mechanisms”, IEEE Micro, pp. 8–23, February 1994.Google Scholar
  3. 3.
    S. Duzellier, G. Berger, “Test Facilities for SEE and Dose Testing”, Radiation Effects on Embedded Systems. Springer 2007. The Netherlands. pp. 201–232.Google Scholar
  4. 4.
    R. Ecoffet, “In-Flight Anomalies on Electronic Devices”, Radiation Effects on Embedded Systems. Springer 2007. The Netherlands. pp. 31–68.Google Scholar
  5. 5.
    IEEE Standard for Environmental Specifications for Spaceborne Computer Modules, March 1997.Google Scholar
  6. 6.
    JEDEC Standard JESD89A, “Measurement and Reporting of Alpha Particle and Terrestrial Cosmic Ray-Induced Soft Errors in Semiconductor Devices”, October 2006.Google Scholar
  7. 7.
    JEDEC Standard JESD57, “Test Procedures for the Measurement of Single-Event Effects in Semiconductor Devices from Heavy Ion Irradiation”, December 1996.Google Scholar
  8. 8.
    S. Buchner, P. Marshall, S. Kniffin, K. LaBel, “Proton Test Guideline Development – Lessons Learned”, NASA/Goddard Space Flight Center, NEPP, August 2002.Google Scholar
  9. 9.
    European Space Agency, “Single Event Effects Test Method and Guidelines”, October 1995.Google Scholar
  10. 10.
    R. Velazco, S. Rezgui, R. Ecoffet, “Predicting Error Rate for Microprocessor-Based Digital Architectures Through C.E.U. (Code Emulating Upsets) Injection”, IEEE Transactions on Nuclear Science, Vol. 47, No. 6, pp. 2405–2411, December 2000.Google Scholar
  11. 11.
    R. Velazco, B. Martinet, G. Auvert, “Laser Injection of Spot Effects on Integrated Circuits”, 1st Asian Test Symposium, pp. 158–163, November 1992.Google Scholar
  12. 12.
    P. Fouillat, V. Pouget, D. Lewis, S. Buchner, D. McMorrow, “Investigation of Single-Event Transients in Fast Integrated Circuits with a Pulsed Laser”, International Journal of High Speed Electronics and Systems, Vol. 14, No. 2, pp. 327–339, 2004.CrossRefGoogle Scholar
  13. 13.
    F. Miller, N. Buard, T. Carrière, R. Dufayel, R. Gaillard, P. Poirot, J. M. Palau, B. Sagnes, P. Fouillat, “Effects of Beam Spot Size on the Correlation Between Laser and Heavy Ion SEU Testing”, IEEE Transactions on Nuclear Science, Vol. 15, No. 6, pp. 3708–3715, December 2004.CrossRefGoogle Scholar
  14. 14.
    D. Powell, J. Arlat, Y. Crouzet, “Estimators for Fault Tolerance Coverage Evaluation”, IEEE Transactions on Computers, Vol. 44, No. 2, pp. 261–274, February 1995.zbMATHCrossRefGoogle Scholar
  15. 15.
    J. Arlat, A. Costes, Y. Crouzet, J. C. Laprie, D. Powell, “Fault Injection and Dependability Evaluation of Fault-Tolerant Systems”, IEEE Transactions on Computers, Vol. 42, No. 8, pp. 913–923, August 1993.CrossRefGoogle Scholar
  16. 16.
    H. Maderia et al. “RIFLE: a general purpose pin-level fault injector”, Proceedings of the First European Dependable Computing Conference, Berlin, Germany, October 1994, pp. 199–216.Google Scholar
  17. 17.
    P. Folkesson, S. Svensson, J. Karlsson, “A comparison of simulation based and scan chain implemented fault injection (SCIFI)”, Proceedings of FTCS-28, IEEE Computer Society Press, Munich, June 1998, pp. 284–293.Google Scholar
  18. 18.
    O. Gunnetlo, J. Karlsson, J. Tonn, “Evaluation of error detection schemes using fault injection by heavy-ion radiation”, Proceedings of the 19th Ann. Int’l Symp. Fault-Tolerant Computing, IEEE CS Press, Los Alamitos, CA, 1989, pp. 340–347.Google Scholar
  19. 19.
    J. Arlat, M. Aguera, L. Amat, Y. Crouzet, J. C. Fabre, J. C. Laprie, E. Martins, D. Powell, “Fault Injection for Dependability Validation: A Methodology and some Applications”, IEEE Transactions on Software Engineering, Vol. 16. No. 2, pp. 166–182, February 1990.CrossRefGoogle Scholar
  20. 20.
    M. C. Hsueh, T. K. Tsai, R. K. Iyer, “Fault Injection Techniques and Tools”, IEEE Computer, Vol. 30, No. 4, pp. 75–82, April 1997.CrossRefGoogle Scholar
  21. 21.
    G. Kanawati, N. A. Kanawati, J. A. Abraham, “FERRARI: A Flexible Software-Based Fault and Error Injection System”, IEEE Transactions on Computers, Vol. 44, No. 2, pp. 248–260, February 1995.zbMATHCrossRefGoogle Scholar
  22. 22.
    J. Carreira, H. Madeira, J. G. Silva, “Xception: A Technique for the Experimental Evaluation of Dependability in Modern Computers”, IEEE Transactions on Software Engineering, Vol. 24, No. 2, pp. 125–136, February 1998.CrossRefGoogle Scholar
  23. 23.
    T. Jarboui, J. Arlat, Y. Crouzet, K. Kanoun, T. Marteau, “Analysis of the effects of real and injected software faults: Linux as a case study”, IEEE Proceedings of 2002 Pacific Rim international Symposium on Dependable Computing (PRDC’02), 2002.Google Scholar
  24. 24.
    M. Rebaudengo, M. Sonza Reorda, “Evaluating the Fault Tolerance Capabilities of Embedded Systems via BDM”, 17th IEEE VLSI Test Symposium, pp. 452–457, Dana Point, USA, April, 1999.Google Scholar
  25. 25.
    IEEE-ISTO 5001-2003, “The Nexus Forum™ standard for a global embedded processor debug interface”, version 2.0, 2003.Google Scholar
  26. 26.
    A. V. Fidalgo, G. R. Alves, J. M. Ferreira, “Real Time Fault Injection Using Enhanced OCD – A Performance Analysis”, 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT), 2006.Google Scholar
  27. 27.
    J. Peng, J. Ma, B. Hong, C. Yuan, “Validation of Fault Tolerance Mechanisms of an Onboard System”, 1st International Symposium on Systems and Control in Aerospace and Astronautics (ISSCAA), pp. 1230–1234, January 2006.Google Scholar
  28. 28.
    M. Portela-García, M. García-Valderas, C. López-Ongil, L. Entrena, “An Efficient Solution to Evaluate SEU Sensitivity in Digital Circuits with Embedded RAMs”, XXI Conference on Design of Circuits and Integrated Systems (DCIS’06), November 2006.Google Scholar
  29. 29.
    P. Kenterlis, N. Kranitis, A. Paschalis, D. Gizopoulus, M. Psarakis, “A Low-Cost SEU Fault Emulation Platform for SRAM-Based FPGAs”, 12th IEEE International On-Line Testing Symposium, pp. 235–241, July 2006.Google Scholar
  30. 30.
    M. Alderighi, F. Casini, S. D’Angelo, M. Mancini, A. Marmo, S. Pastore, G. R. Sechi, “A Tool for Injecting SEU-like Faults into the Configuration Control Mechanism of Xilinx Virtex FPGAs”, 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2003.Google Scholar
  31. 31.
    M. Alderighi, F. Casini, S. D’Angelo, M. Mancini, S. Pastore, G. R. Sechi, R. Weigand, “Evaluation of Single Event Upset Mitigation Schemes for SRAM Based FPGAs Using the FLIPPER Fault Injection Platform”, 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 105–113, 2007.Google Scholar
  32. 32.
    K. T. Cheng, S. Y. Huang, W. J. Dai, “Fault emulation: a new approach to fault grading”, Proceedings of the International Conference on Computer-Aided Design, pp. 681–686, 1995.Google Scholar
  33. 33.
    L. Antoni, R. Leveugle, B. Feher, “Using Run-Time Reconfiguration for Fault Injection in HW Prototypes”, IEEE Int. Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 245–253, 2002.Google Scholar
  34. 34.
    M. Aguirre, J. N. Tombs, F. Muñoz, V. Baena, A. Torralba, A. Fernandez-Leon, F. Tortosa, D. Gonzalez-Gutierrez, “An FPGA based hardware emulator for the insertion and analysis of Single Event Upsets in VLSI Designs”, Radiation Effects on Components and Systems Workshop, September 2004.Google Scholar
  35. 35.
    J. H. Hong, S. A. Hwang, C. W. Wu, “An FPGA-Based Hardware Emulator for Fast Fault Emulation”, MidWest Symposium on Circuits and Systems, 1996.Google Scholar
  36. 36.
    P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante, “Exploiting Circuit Emulation for Fast Hardness Evaluation”, IEEE Transactions on Nuclear Science, Vol. 48, No. 6, 2001.Google Scholar
  37. 37.
    C. López-Ongil, M. García-Valderas, M. Portela-García, L. Entrena, “Autonomous Fault Emulation: A New FPGA-based Acceleration System for Hardness Evaluation”, IEEE Transactions on Nuclear Science, Vol. 54, Issue 1, Part 2, pp. 252–261, February 2007.Google Scholar
  38. 38.
    M. Violante, “Accurate Single-Event-Transient Analysis via Zero-Delay Logic Simulation”, IEEE Transactions on Nuclear Science, Vol. 50, No. 6, December 2003.Google Scholar
  39. 39.
    M. García Valderas, R. Fernández Cardenal, C. López Ongil, M. Portela García, L. Entrena. “SET emulation under a quantized delay model”, Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFTS), pp. 68–78, September 2007.Google Scholar
  40. 40.
    F. Lima, S. Rezgui, L. Carro, R. Velazco, R. Reis, “On the use of VHDL simulation and emulation to derive error rates”, Proceedings of 6th Conference on Radiation and Its Effects on Components and Systems (RADECS’01), Grenoble, September 2001.Google Scholar
  41. 41.
    F. Faure, P. Peronnard, R. Velazco, R. Ecoffet, “THESIC+, a flexible system for SEE testing”, Proceedings of RADECS Workshop, [September 19–20, 2002, Padova], pp. 231–234.Google Scholar
  42. 42.
    D. Lewis, V. Pouget, F. Beaudoin, P. Perdu, H. Lapuyade, P. Fouillat, A. Touboul, “Backside Laser Testing of ICs for SET Sensitivity Evaluation”, IEEE Transactions on Nuclear Science, Vol. 48, Issue 6, Part 1, pp. 2193–2201, December 2001.CrossRefGoogle Scholar
  43. 43.
    F. Faure, R. Velazco, P. Peronnard, “Single-Event-Upset-Like Fault Injection: A Comprehensive Framework”, IEEE Transactions on Nuclear Science, Vol. 52, Issue 6, Part 1, pp. 2205–2209, December 2005.CrossRefGoogle Scholar
  44. 44.
    P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante, “FPGA-Based Fault Injection for Microprocessor Systems”, IEEE Asian Test Symposium, pp. 304–309, 2001.Google Scholar
  45. 45.
    M. Nicolaidis, “Emulation/Simulation d’un circuit logique”, French patent, filed February 25 2005, issued October 12 2007.Google Scholar
  46. 46.
    M. G. Valderas, P. Peronnard, C. Lopez-Ongil, R. Ecoffet, F. Bezerra, R. Velazco, “Two Complementary Approaches for Studying the Effects of SEUs on Digital Processors”, IEEE Transactions on Nuclear Science, Vol. 54, Issue 4, Part 2, pp. 924–928, August 2007.CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  1. 1.Electronic Technology DepartmentCarlos III University of MadridMadridSpain
  2. 2.TIMA (CNRS, Grenoble INP, UJF)GrenobleFrance

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