Advertisement

Closing the Gap Between Electrical and Physical Design: The Layout-Aware Solution

  • Rafael Castro-Lόpez
  • Elisenda Roca
  • Francisco V. Fernández
Chapter

Abstract

Iterations between separate phases in any procedural design process, usually a by-product of unexpected (or, simply, very complex to consider) adverse effects, clearly play against any time-to-market requirements. In analog integrated circuit (IC) design, going back and forth between electrical and physical synthe- sis to counterbalance layout-induced performance degradations needs to be thus avoided as much as possible. One possible solution involves the integration of the 1 traditionally separated electrical and physical synthesis phases, by including layout- induced effects, in the form of layout parasitics, right into the electrical synthesis phase, in what has been called parasitic-aware synthesis. This solution, as such, is not yet complete since there are geometric requirements (minimization of the occu- pied area or fulfillment of certain layout aspect ratio, among others), whose effects on the resulting parasitics are not usually considered during electrical synthesis. In this chapter, a layout-aware solution that tackles both geometric and parasitic-aware electrical synthesis is proposed. This technique uses a combination of simulation- based optimization, procedural layout generation, exhaustive geometric evaluation algorithms, and several mechanisms for parasitic estimation. Thanks to the nature of this combination, the solution benefits from, and also fosters, reuse of analog intellectual property (IP) blocks. Several detailed design examples are provided.

Keywords

Leaf Node Analog Circuit Area Loss Layout Generation Circuit Sizing 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Int. Technology Roadmap for Semiconductors. [Online]. Available: http://public.itrs.net, 2005.
  2. 2.
    MEDEA+ Design Automation Roadmap. [Online]. Available: http://www.medeaplus.org, 2007.
  3. 3.
    M. Degrauwe, O. Nys, and E. Dijkstra, “IDAC: An interactive design tool for analog CMOS circuits,” IEEE J. Solid-State Circuits, vol. SSC-22, no. 6, pp. 1106 – 1116, Dec 1987.CrossRefGoogle Scholar
  4. 4.
    J. Conway and G. Schrooten, “An automatic layout generator for analog circuits,” in European Design Automation Conference, Mar 1992, pp. 513 – 519.Google Scholar
  5. 5.
    R. Castro-Lopez, F. Fernandez, and F. Medeiro, “Generation of technology-independent retargetable analog blocks,” Analog Integrated Circuits and Signal Processing, vol. 3, no. 2, pp. 157 – 170, Nov 2002.CrossRefGoogle Scholar
  6. 6.
    N. Jangkrajarng, S. Bhattacharya, and R. Hartono, “IPRAIL – intellectual property reuse-based analog IC layout automation,” Integration, VLSI J., Nov 2003.Google Scholar
  7. 7.
    S. Bhattacharya, N. Jangkrajarng, and C. Shi, “Multilevel symmetry-constraint generation for retargeting large analog layouts,” IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. 25, no. 6, pp. 945 – 960, Jun 2006.CrossRefGoogle Scholar
  8. 8.
    S. Bhattacharya, N. Jangkrajarng, and C. Shi, “Template-driven parasitic-aware optimization of analog integrated circuit layouts,” in ACM/IEEE Design Automation Conference (DAC), Jun 2005, pp. 644 – 647.Google Scholar
  9. 9.
    N. Jangkrajarng, L. Zhang, S. Bhattacharya, N. Kohagen, and C. Shi, “Template-based parasitic-aware optimization and retargeting of analog and RF integrated circuit layouts,” in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov 2006, pp. 342 – 348.Google Scholar
  10. 10.
    J. Harvey, M. Elmasry, and B. Leung, “STAIC: An interactive framework for synthesizing CMOS and BiCMOS analog circuits,” IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. 11, no. 1, pp. 1402 – 1417, Nov 1992.CrossRefGoogle Scholar
  11. 11.
    G. Gielen, H. Walscharts, and W. Sansen, “Analog circuit design optimization based on symbolic simulation and simulated annealing,” IEEE J. Solid-State Circuits, vol. 25, no. 3, pp. 707 – 713, Jun 1990.CrossRefGoogle Scholar
  12. 12.
    P. Maulik, L. Carley, and D. Allstot, “Sizing of cell-level analog circuits using constrained optimization techniques,” IEEE J. Solid-State Circuits, vol. 28, no. 3, pp. 233 – 241, Mar 1993.CrossRefGoogle Scholar
  13. 13.
    M. Hershenson, S. Boyd, and T. Lee, “Optimal design of a CMOS op-amp via geometric programming,” IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. 20, no. 1, pp. 1–21, Jan 2001.CrossRefGoogle Scholar
  14. 14.
    F. Fernández, A. Rodríguez, and J. L. Huertas, Symbolic Analysis Techniques: Applications to Analog Design Automation. IEEE Press, New York, 1997.Google Scholar
  15. 15.
    C. Shi and X.-D. Tan;, “Canonical symbolic analysis of large analog circuits with determinant decision diagrams,” IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. 19, no. 1, pp. 1 – 18, Jan 2000.CrossRefGoogle Scholar
  16. 16.
    P. Vancorenland, G. V. der Plas, M. Steyaert, G. Gielen, and W. Sansen, “A layout-aware synthesis methodology for RF circuits,” in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov 2001, pp. 358 – 362.Google Scholar
  17. 17.
    W. Nye, D. C. Riley, A. Sangiovanni-Vincentelli, and A. L. Tits, “DELIGHT.SPICE: An optimization-based system for the design of integrated circuits,” IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. 7, no. 4, pp. 501 – 519, Apr 1988.CrossRefGoogle Scholar
  18. 18.
    G. Stehr, M. Pronath, F. Schenkel, H. Graeb, and K. Antreich, “Initial sizing of analog integrated circuits by centering within topology-given implicit specifications,” in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov 2003, pp. 241 – 246.Google Scholar
  19. 19.
    R. Phelps, M. Krasnicki, R. Rutenbar, L. Carley, and J. Hellums, “Anaconda: simulation-based synthesis of analog circuits via stochastic pattern search,” IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. 19, no. 6, pp. 703 – 717, Jun 2000.CrossRefGoogle Scholar
  20. 20.
    F. Medeiro, A. Pérez-Verdú, and A. Rodríguez-Vázquez, Top-Down Design of High-Performance Sigma-Delta Modulators. Kluwer, Dordrecht, 1999.Google Scholar
  21. 21.
    E. Ochotta, R. Rutenbar, and L. Carley, “Synthesis of high-performance analog circuits in ASTRX/OBLX,” IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. 15, no. 3, pp. 273 – 294, Mar 1996.CrossRefGoogle Scholar
  22. 22.
    H. Chang, E. Liu, R. Neff, E. Felt, and E. Malavasi, Top-Down, Constraint-Driven Design Methodology for Analog Integrated Circuits. Kluwer, Dordrecht, 97.Google Scholar
  23. 23.
    J. Cohn, D. Garrod, R. Rutenbar, and L. Carley, “KOAN/ANAGRAM II: new tools for device-level analog placement and routing,” IEEE J. Solid-State Circuits, vol. 26, no. 3, pp. 330 – 342, Mar 1991.CrossRefGoogle Scholar
  24. 24.
    K. Lampaert, G. Gielen, and W. Sansen, Analog Layout Generation for Performance and Manufacturability. Kluwer, Dordrecht, 1999.Google Scholar
  25. 25.
    M. Dessouky and M. Louerat, “A layout approach for electrical and physical design integration of high-performance analog circuits,” in IEEE First International Symposium on Quality Electronic Design (ISQED), Mar 2000, pp. 291 – 298.Google Scholar
  26. 26.
    H. Onodera, H. Kanbara, and K. Tamaru, “Operational-amplifier compilation with performance optimization,” IEEE J. Solid-State Circuits, vol. 25, no. 2, pp. 466 – 473, Apr 1990.CrossRefGoogle Scholar
  27. 27.
    A. Agarwal, H. Sampath, V. Yelamanchili, and R. Vemuri, “Fast and accurate parasitic capacitance models for layout-aware synthesis of analog circuits,” in Design Automation Conference and Test in Europe Conference (DATE), Mar 2004, pp. 145 – 150.Google Scholar
  28. 28.
    M. Ranjan, W. Verhaegen, A. Agarwal, H. Sampath, R. Vemuri, and G. Gielen, “Fast, layout-inclusive analog circuit synthesis using pre-compiled parasitic-aware symbolic performance models,” in Design Automation Conference and Test in Europe Conference (DATE), vol. 1, Feb 2004, pp. 604 – 609.Google Scholar
  29. 29.
    A. Pradhan and R. Vemuri, “Efficient synthesis of a uniformly spread layout aware pareto surface for analog circuits,” in 22nd International Conference on VLSI Design, Dec 2009, pp. 131 – 136.Google Scholar
  30. 30.
    R. Castro-Lopez, O. Guerra, E. Roca, and F. Fernandez, “An integrated layout-synthesis approach for analog ics,” Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 27, no. 7, pp. 1179 – 1189, Jul 2008.CrossRefGoogle Scholar
  31. 31.
    R. P. Brent, Algorithms for Minimization Without Derivatives. Prentice Hall, Englewood Cliffs, NJ, 2002.MATHGoogle Scholar
  32. 32.
    G. Zhang, A. Dengi, R. Rohrer, R. Rutenbar, and L. Carley, “A synthesis flow toward fast parasitic closure for radio-frequency integrated circuits,” in ACM/IEEE Design Automation Conference (DAC), 2004, pp. 155 – 158.Google Scholar
  33. 33.
    Virtuoso Parameterized Cell Reference, 4th ed., Cadence Des. Syst. Inc., San Jose, CA, 2000.Google Scholar
  34. 34.
    SKILL Language Reference, 6th ed., Cadence Des. Syst. Inc., San Jose, CA, 2004.Google Scholar
  35. 35.
    R. Otten, “Automatic floorplan design,” in ACM/IEEE Design Automation Conference (DAC), 1982, pp. 261 – 267.Google Scholar
  36. 36.
    L. Stockmeyer, “Optimal orientations of cells in slicing floorplan designs.” Inf. Control, vol. 57, no. 2/3, pp. 91 – 101, May/Jun 1983.Google Scholar
  37. 37.
    H. Koh, C. Sequin, and P. Gray, “OPASYN: a compiler for CMOS operational amplifiers,” IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. 9, no. 2, pp. 113 – 125, Feb 1990.CrossRefGoogle Scholar
  38. 38.
    R. Naiknaware and T. Fiez, “Automated hierarchical CMOS analog circuit stack generation with intramodule connectivity and matching considerations,” IEEE J. Solid-State Circuits, vol. 34, no. 3, pp. 304 – 303, Mar 1999.Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  • Rafael Castro-Lόpez
    • 1
  • Elisenda Roca
  • Francisco V. Fernández
  1. 1.Instituto de Microelectrόnica de SevillaIMSE-CNM-CSIC and University of SevilleSevilleSpain

Personalised recommendations