Device-Level Topological Placement with Symmetry Constraints



The traditional way of approaching placement problems in computer-aided design (CAD) tools for analog layout is to explore an extremely large search space of feasible or unfeasible placement configurations (called flat representations of the layout), where the cells are moved in the chip plane by a stochastic optimizer – like simulated annealing or a genetic algorithm. This chapter discusses the possible use in analog placement problems with symmetry constraints of topological representations of the layout, encoding systems that are not restricted to slicing floorplan topologies. First, the chapter gives an overview of several data structures that may be used in the evaluation of various topological representations of the layout – therefore, in building the placement from the layout encoding. Afterwards, the chapter presents a subset of sequence-pairs – called “symmetric-feasible” – that allows to take into account the presence of an arbitrary number of symmetry groups of devices during the exploration of the solution space. Alternatively, the possible use of tree representations instead of “symmetric-feasible” sequence-pairs is also discussed. The computation times exhibited by the topological approaches are significantly better than those of the placement algorithms using the traditional exploration strategy based on flat representations, while preserving a similar quality of the placement solutions.


Symmetry Group Binary Tree Directed Acyclic Graph Priority Queue Symmetry Constraint 


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© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  1. 1.Department of Computer Science and Information SystemsSouthern Utah UniversityCedar CityUSA

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