Application-Specific Routing Algorithms for Low Power Network on Chip Design

  • Maurizio Palesi
  • Rickard Holsmark
  • Shashi Kumar
  • Vincenzo Catania


In the last few years, Network-on-Chip (NoC) has emerged as a dominant paradigm for synthesis of a multi-core Systems-on-Chip (SoC). A future NoC architecture must be general enough to allow volume production and must have features for specialization and configuration to match and meet the application’s power and performance requirements. This chapter describes how one important aspect, namely the routing algorithm, can be optimized in such NoC platforms. Routing algorithm has a major effect on the performance (packet latency and throughput) as well as power consumption of NoC. A methodology to develop efficient and deadlock free routing algorithms which are specialized for an application or a set of concurrent applications is presented. The methodology, called application-specific routing algorithms (APSRA), exploits the application-specific information regarding pairs of cores which communicate and other pairs which never communicate in the NoC platform. This information is used to maximize the adaptivity of the routing algorithm without compromising the important property of deadlock freedom. The chapter also presents an extensive comparison between the routing algorithms generated using APSRA methodology and general purpose deadlock-free routing algorithms. The simulation-based evaluations are performed using both synthetic traffic and traffic from real applications. The comparison embraces several performance indices such as degree of adaptiveness, average delay, throughput, power dissipation, and energy consumption. In spite of an adverse impact on router architecture, it is shown that the higher adaptivity of APSRA leads to significant improvements in both routing performance and energy consumption.


Power Dissipation Virtual Channel Communication Graph Silicon Area Traffic Scenario 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 1.
    Ascia, G., Catania, V., Palesi, M.: Multi-objective mapping for mesh-based NoC architectures. In: Second IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, pp. 182–187. Stockholm, Sweden (2004)Google Scholar
  2. 2.
    Ascia, G., Catania, V., Palesi, M., Patti, D.: Implementation and analysis of a new selection strategy for adaptive routing in networks-on-chip. IEEE Transactions on Computers 57(6), 809–820 (2008)MathSciNetCrossRefGoogle Scholar
  3. 3.
    Avresky, D.R., Shubranov, V., Horst, R., Mehra, P.: Performance evaluation of the ServerNetR SAN under self-similar traffic. In: International Symposium on Parallel and Distributed Processing, pp. 143–149 (1999)Google Scholar
  4. 4.
    Boppana, R.V., Chalasani, S.: A comparison of adaptive wormhole routing algorithms. In: International Symposium on Computer Architecture, pp. 351–360. San Diego, CA (1993)Google Scholar
  5. 5.
    Boppana, R.V., Chalasani, S.: Fault-tolerant wormhole routing algorithms for mesh networks. IEEE Transactions on Computers 44(7), 848–864 (1995)CrossRefMATHGoogle Scholar
  6. 6.
    Chatha, K., Srinivasan, K., Konjevod, G.: Approximation algorithms for design of application specific network-on-chip architectures. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (2008)Google Scholar
  7. 7.
    Chen, K.H., Chiu, G.M.: Fault-tolerant routing algorithm for meshes without using virtual channels. Journal of Information Science and Engineering 14(4), 765–783 (1998)Google Scholar
  8. 8.
    Cherkasova, L., Kotov, V., Rokicki, T.: Fibre channel fabrics: Evaluation and design. In: Hawaii International Conference on System Sciences, pp. 53–58 (1996)Google Scholar
  9. 9.
    Chien, A.A., Kim, J.H.: Planar-adaptive routing: Low-cost adaptive networks for multiprocessors. Journal of the ACM 42(1), 91–123 (1995)CrossRefMATHGoogle Scholar
  10. 10.
    Chiu, G.M.: The odd-even turn model for adaptive routing. IEEE Transactions on Parallel Distributed Systems 11(7), 729–738 (2000)CrossRefGoogle Scholar
  11. 11.
    Dally, W.J., Seitz, C.: The torus routing chip. Journal of Distributed Computing 1(3), 187–196 (1986)CrossRefGoogle Scholar
  12. 12.
    Dally, W.J., Seitz, C.: Deadlock-free message routing in multiprocessor interconnection networks. IEEE Transactions on Computers C(36), 547–553 (1987)Google Scholar
  13. 13.
    Duato, J.: A new theory of deadlock-free adaptive routing in wormhole networks. IEEE Transactions on Parallel and Distributed Systems 4(12), 1320–1331 (1993)CrossRefGoogle Scholar
  14. 14.
    Duato, J.: A necessary and sufficient condition for deadlock-free routing in wormhole networks. IEEE Transactions on Parallel and Distributed Systems 6(10), 1055–1067 (1995)CrossRefGoogle Scholar
  15. 15.
    Duato, J., Lysne, O., Pang, R., Pinkston, T.M.: Part I: A theory for deadlock-free dynamic network reconfiguration. IEEE Transactions on Parallel and Distributed Systems 16(5), 412–427 (2005)CrossRefGoogle Scholar
  16. 16.
    Fazzino, F., Palesi, M., Patti, D.: Noxim: Network-on-Chip simulator.
  17. 17.
    Gindin, R., Cidon, I., Keidar, I.: NoC-based FPGA: architecture and routing. In: International Symposium on Networks-on-Chip, pp. 253–264. IEEE Computer Society (2007)Google Scholar
  18. 18.
    Glass, C.J., Ni, L.M.: The turn model for adaptive routing. Journal of the Association for Computing Machinery 41(5), 874–902 (1994)CrossRefGoogle Scholar
  19. 19.
    Goossens, K., Bennebroek, M., Hur, J.Y., Wahlah, M.A.: Hardwired networks on chip in FPGAs to unify functional and configuration interconnects. In: IEEE International Symposium on Networks-on-Chip, pp. 45–54 (2008)Google Scholar
  20. 20.
    Guz, Z., Walter, I., Bolotin, E., Cidon, I., Ginosar, R., Kolodny, A.: Network delays and link capacities in application-specific wormhole NoCs. VLSI Design (2007)Google Scholar
  21. 21.
    Holsmark, R.: Deadlock free routing in mesh networks on chip with regions. Licentiate thesis, Linköping University, Department of Computer and Information Science, The Institute of Technology (2009)Google Scholar
  22. 22.
    Holsmark, R., Kumar, S.: Design issues and performance evaluation of mesh NoC with regions. In: IEEE Norchip, pp. 40–43. Oulu, Finland (2005)Google Scholar
  23. 23.
    Holsmark, R., Kumar, S.: Corrections to Chen and Chiu’s fault tolerant routing algorithm for mesh networks. Journal of Information Science and Engineering 23(6), 1649–1662 (2007)Google Scholar
  24. 24.
    Hu, J., Marculescu, R.: DyAD – smart routing for networks-on-chip. In: ACM/IEEE Design Automation Conference, pp. 260–263. San Diego, CA (2004)Google Scholar
  25. 25.
    Hu, J., Marculescu, R.: Energy- and performance-aware mapping for regular NoC architectures. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 24(4), 551–562 (2005)CrossRefGoogle Scholar
  26. 26.
    Jouraku, A., Koibuchi, M., Amano, H.: L-turn routing: An adaprive routing in irregular networks. Tech. Rep. 59, IEICE (2001)Google Scholar
  27. 27.
    Kim, J., Park, D., Theocharides, T., Vijaykrishnan, N., Das, C.R.: A low latency router supporting adaptivity for on-chip interconnects. In: ACM/IEEE Design Automation Conference, pp. 559–564 (2005)Google Scholar
  28. 28.
    Kumar, S., Jantsch, A., Soininen, J.P., Forsell, M., Millberg, M., Oberg, J., Tiensyrja, K., Hemani, A.: A network on chip architecture and design methodology. In: IEEE Computer Society Annual Symposium on VLSI, p. 117 (2002)Google Scholar
  29. 29.
    Lee, S.E., Bagherzadeh, N.: A high level power model for network-on-chip (NoC) router. Computers and Electrical Engineering 35(6), 837–845 (2009)CrossRefMATHGoogle Scholar
  30. 30.
    Lotfi-Kamran, P., Daneshtalab, M., Lucas, C., Navabi, Z.: BARP-a dynamic routing protocol for balanced distribution of traffic in NoCs. In: ACM/IEEE Design Automation Conference, pp. 1408–1413 (2008)Google Scholar
  31. 31.
    Lysne, O., Pinkston, T.M., Duato, J.: Part II: A methodology for developing deadlock-free dynamic network reconfiguration processes. IEEE Transactions on Parallel and Distributed Systems 16(5), 428–443 (2005)CrossRefGoogle Scholar
  32. 32.
    Mejia, A., Flich, J., Duato, J., Reinemo, S.A., Skeie, T.: Segment-based routing: An efficient fault-tolerant routing algorithm for meshes and tori. In: International Parallel and Distributed Processing Symposium. Rhodos, Grece (2006)Google Scholar
  33. 33.
    Mejia, A., Palesi, M., Flich, J., Kumar, S., Lopez, P., Holsmark, R., Duato, J.: Region-based routing: A mechanism to support efficient routing algorithms in NoCs. IEEE Transactions on Very Large Scale Integration Systems 17(3), 356–369 (2009)CrossRefGoogle Scholar
  34. 34.
    Murali, S., Micheli, G.D.: Bandwidth-constrained mapping of cores onto NoC architectures. In: Design, Automation, and Test in Europe, pp. 896–901. IEEE Computer Society (2004)Google Scholar
  35. 35.
    Ni, L.M., McKinley, P.K.: A survey of wormhole routing techniques in direct networks. IEEE Computer 26, 62–76 (1993)CrossRefGoogle Scholar
  36. 36.
    Nilsson, E., Millberg, M., Oberg, J., Jantsch, A.: Load distribution with the proximity congestion awareness in a network on chip. In: Design, Automation and Test in Europe, pp. 1126–1127. Washington, DC (2003)Google Scholar
  37. 37.
    Palesi, M., Kumar, S., Holsmark, R.: A method for router table compression for application specific routing in mesh topology NoC architectures. In: SAMOS VI Workshop: Embedded Computer Systems: Architectures, Modeling, and Simulation, pp. 373–384. Samos, Greece (2006)Google Scholar
  38. 38.
    Palesi, M., Kumar, S., Holsmark, R., Catania, V.: Exploiting communication concurrency for efficient deadlock free routing in reconfigurable NoC platforms. In: IEEE International Parallel and Distributed Processing Symposium, pp. 1–8. Long Beach, CA (2007)Google Scholar
  39. 39.
    Palesi, M., Holsmark, R., Kumar, S., Catania, V.: Application specific routing algorithms for networks on chip. IEEE Transactions on Parallel and Distributed Systems 20(3), 316–330 (2009)CrossRefGoogle Scholar
  40. 40.
    Palesi, M., Kumar, S., Catania, V.: Bandwidth aware routing algorithms for networks-on-chip platforms. Computers and Digital Techniques, IET 3(11), 413–429 (2009)CrossRefGoogle Scholar
  41. 41.
    Pande, P.P., Grecu, C., Jones, M., Ivanov, A., Saleh, R.: Performance evaluation and design trade-offs for network-on-chip interconnect architectures. IEEE Transactions on Computers 54(8), 1025–1040 (2005)CrossRefGoogle Scholar
  42. 42.
    Sancho, J.C., Robles, A., Duato, J.: A flexible routing scheme for networks of workstations. In: International Symposium on High Performance Computing, pp. 260–267. London, UK (2000)Google Scholar
  43. 43.
    Schroeder, M.D., Birrell, A.D., Burrows, M., Murray, H., Needham, R.M., Rodeheffer, T.L., Satterthwaite, E.H., Thacker, C.P.: Autonet: a high-speed, self-configuring local area network using point-to-point links. IEEE Journal on Selected Areas in Communications 9(8), 1318–1335 (1991)CrossRefGoogle Scholar
  44. 44.
    Shang, L., Peh, L.S., Jha, N.K.: Dynamic voltage scaling with links for power optimization of interconnection networks. In: 9th International Symposium on High-Performance Computer Architecture, p. 91. IEEE Computer Society (2003)Google Scholar
  45. 45.
    Stensgaard, M.B., Sparsø, J.: ReNoC: A network-on-chip architecture with reconfigurable topology. In: IEEE International Symposium on Networks-on-Chip, pp. 55–64 (2008)Google Scholar
  46. 46.
    Upadhyay, J., Varavithya, V., Mohapatra, P.: A traffic-balanced adaptive wormhole routing scheme for two-dimensional meshes. IEEE Transactions on Computers 46(2), 190–197 (1997)CrossRefGoogle Scholar
  47. 47.
    Varatkar, G., Marculescu, R.: Traffic analysis for on-chip networks design of multimedia applications. In: ACM/IEEE Design Automation Conference, pp. 510–517 (2002)Google Scholar
  48. 48.
    Wolkotte, P.T., Smit, G.J., Kavaldjiev, N., Becker, J.E., Becker, J.: Energy model of networks-on-chip and a bus. In: International Symposium on System-on-Chip, pp. 82–85 (2005)Google Scholar
  49. 49.
    Wu, J., Jiang, Z.: Extended minimal routing in 2D meshes with faulty blocks. In: International Conference on Distributed Computing Systems, pp. 49–54 (2002)Google Scholar
  50. 50.
    Ye, T.T., Benini, L., Micheli, G.D.: Packetization and routing analysis of on-chip multiprocessor networks. Journal of System Architectures 50(2–3), 81–104 (2004)CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  • Maurizio Palesi
    • 1
  • Rickard Holsmark
  • Shashi Kumar
  • Vincenzo Catania
  1. 1.Dipartimento di Ingegneria Informatica e delle TelecomunicazioniUniversity of CataniaCataniaItaly

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